computer-implemented methods to hide selected installed functions from a multifunctional instruction

专利摘要:
FUNCTION OF VIRTUALIZATION OF FUNCTION TO CONSULT A PROCESSOR'S FUNCTION. The selected installed function of a multi-function instruction is hidden so that even if a processor is able to perform the hidden installed function, the availability of the hidden function is hidden so that it responds to the multi-function instruction by consulting the availability of the functions, only non-hidden functions are reported as installed.
公开号:BR112012033817B1
申请号:R112012033817-0
申请日:2010-11-08
公开日:2020-12-01
发明作者:Dan Greiner；Damian Osisek；Timothy Slegel
申请人:International Business Machines Corporation；
IPC主号:

专利说明:

FIELD OF THE INVENTION
[0001] The present invention relates to computer systems and more particularly the instructional functionality of the computer system processor. BACKGROUND
[0002] Trademarks: IBM® and a registered trademark of International Business Machines Corporation, Armonk, New York, USA, S / 390, z900 and z10 and other product names may be trademarks or product names of International Business Machines Corporation or other companies.
[0003] IBM created through the work of many highly talented engineers starting with machines known as the IBM® 360 System in the 1960s to the present, a special architecture that, due to its essential nature for a computing system, became known as “the mainframe” whose operating principles determine the architecture of the machine by describing the instructions that can be performed on the “mainframe” implementation of the instructions that had been invented by IBM inventors and adopted, due to their significant contribution to improve the state of the computing machine represented by the "mainframe", as significant contributions by including it in the IBM Operating Principles as stated over the years. The eighth Edition of IBM® z / Architecture® Principles of Operation that was published in February 2009 became the standard published reference as SA22-7832-07 and is incorporated into IBM's z10® mainframe servers.
[0004] With reference to figure 1, representative components of a state-of-the-art host computer system, 50, are depicted. Other component arrangements can also be employed in a computer system, which are well known in the art. The representative Host Computer, 50, comprises one or more CPUs 1 in communication with main storage (Computer memory 2) as well as I / O interfaces for storage devices 11 and networks 10 to communicate with other computers or SANs and the like. CPU 1 conforms to an architecture having a set of architected instructions and architected functionality. CPU 1 can have Dynamic Address Translation (DAT) 3 to transform program addresses (virtual addresses) into real memory addresses. A DAT typically includes a Translation Lookaside Buffer (TLB) 7 for translation caching so that subsequent access to computer memory block 2 does not require the address translation delay. Typically, a cache 9 is used between Computer Memory 2 and Processor 1. Cache 9 can be hierarchical having a large cache available for more than one CPU and smaller and faster caches (lower level) between the large cache and each CPU. In some implementations, the lower level caches are divided to provide separate low level caches for data access and instruction search. In one embodiment, an instruction is fetched from memory 2 by a search unit 4 through a cache 9. The instruction is decoded into an instruction decode unit 6 and is sent (with other instructions in some embodiments) to execution units. instruction 8. Typically, several execution units 8 are employed, for example, an arithmetic execution unit, a floating point execution unit and a branch instruction execution unit. The instruction is carried out by the executing unit, accessing operands from records specified in the instruction or memory as needed. If an operator is to be accessed (loaded or stored) from memory 2, a load storage unit 5 typically handles access under control of the instruction being executed. Instructions can be executed in hardware circuits or in internal micro-code (firmware) or by a combination of both.
[0005] In figure 1B, an example of a host computer system emulated from the state of the art 21 is provided that emulates a host computer system 50 of a host architecture. In the emulated Host Computer system 21, the Host processor (CPU) 1 is an emulated Host processor (or virtual Host processor) and comprises an emulation processor 27 having a native instruction set architecture different from that of Host Computer 50 processor 1 The emulated Host Computer system 21 has memory 22 access to the emulation processor 27. In the example embodiment, Memory 27 is divided into a portion of Host Computer Memory 2 and a portion of emulation Routines 23. Computer Memory Host 2 is available for emulated 21 Host Computer programs according to the Host Computer Architecture. Emulation Processor 27 executes native instructions from a set of instructions architected from an architecture different from that of emulated processor 1, the native instructions obtained from the memory of Emulation Routines 23 and can access a Host instruction to execute from a program in Host Computer Memory 2 for employing one or more instruction (s) obtained in a Sequence & Access / Decoding routine that can decode the Host instruction (s) accessed to determine a routine execution of native instruction to emulate the function of the Host instruction accessed. Other facilities that are defined for the architecture of the Host Computer System 50 can be emulated by Architectural Facility Routines, including such facilities as General Purpose Records, Control Records, Dynamic Address Translation and I / O Subsystem and Cache support processor, for example. Emulation routines can also take advantage of the functionality available in Emulation Processor 27 (such as general logs and dynamic translation of virtual addresses) to improve the performance of Emulation Routines. Special hardware and unloading mechanisms can also be provided to assist processor 27 in emulating the function of Host Computer 50.
[0006] On a mainframe, engineered machine instructions are used by programmers, usually current "C" programmers often through a compiler application. These instructions stored in the storage medium can be executed natively on an IBM z / Architecture Server, or alternatively on machines running other architectures. They can be emulated on existing and future IBM mainframe servers and other IBM machines (for example, pSeries® servers and xSeries® servers. They can run on machines that run Linux on a wide variety of machines using hardware manufactured by IBM®, Intel ®, AMD ™, Sun Microsystems and others In addition to running on that hardware under a Z / Architecture®, Linux can be used as well as machines that use emulation as described at http://www.turbohercules.com, http: // www .hercules-390.org and http://funsoft.com In emulation mode, emulation software is run by a native processor to emulate the architecture of an emulated processor.
[0007] Native processor 27 typically runs emulation software 23 comprising firmware or a native operating system to perform emulation of the emulated processor. The emulation software 23 is responsible for seeking and executing instructions from the emulated processor architecture. The emulation software 23 maintains an emulated program counter for tracking instruction limits. Emulation software 23 can fetch one or more emulated machine instructions at a time and convert one or more emulated machine instructions into a corresponding group of native machine instructions for execution by the native processor 27. These converted instructions can be cached so that a faster conversion can be carried out. However, the emulation software must maintain the architectural rules of the emulated processor architecture to ensure that operating systems and applications written for the emulated processor operate correctly. In addition, the emulation software must provide features identified by the architecture of the emulated processor 1 including, but not limited to control registers, general purpose registers, floating point registers, dynamic address translation function including segment tables and index tables. pages, for example, interrupt mechanisms, context change mechanisms, Time of Day (TOD) clocks and interfaces designed for I / O subsystems so that an operating system or application program designed to run on the emulated processor, can be run on the native processor using the emulation software.
[0008] A specific instruction being emulated and decoded, and a subroutine called to perform the function of the individual instruction. An emulation software function 23 emulating a function of an emulated processor 1 is implemented, for example, in a "C" subroutine or driver, or some other method of providing a driver for specific hardware as will be understood in the knowledge of those skilled in the art after understanding the description of the preferred embodiment. Various hardware and software emulation patents including, but not limited to, US 5551013 for a "Multiprocessor for hardware emulation" by Beausoleil et al. And US6009261: "Preprocessing of sorted target routines for emulating incompatible instructions on a target processor" by Scalzi and others ; and US5574873: "Decoding guest instruction to directly access emulation routines that emulate the guest instructions" by Davidian and others; US6308255: "Symmetrical multiprocessing bus and chipset used for coprocessor support allowing non-native code to run in a system", by Gorishek and others; and US6463582: "Dyamic optimizing object code translator for architecture emulation and dynamic optimizing object code translation method by Lethin” and others; and US5790825: "Method for emulating guest instructions on a host computer through dynamic recompilation of host instructions". references illustrate a variety of known methods for obtaining emulation of an instruction format designed for a different machine for a target machine available to those skilled in the art, as well as those of commercial software techniques used by those referenced above.
[0009] In US publication no. US 2009/0222814 A1, published on September 3, 2009, Astrand, “Selective exposure to USB device functionality for a virtual machine”, a virtual machine application (VM) can run a host operating system (OS) and allow the Host OS connects to US devices connected to a computer. The VM application can filter the functions associated with the USB device so that only some of the functions of the USB device are exposed to the host OS. SUMMARY
[0010] In one embodiment, installed functions selected from a multi-function instruction are hidden, the architectural multi-function instruction to perform a function from a plurality of installed functions, the concealment comprising setting a value that controls the availability of installed functions for a multi-function instruction from a Host Computer comprising one or more processors, a processor having a first plurality of installed functions from the multi-function instruction, the first plurality of installed functions comprising one or more first installed functions and one or more second installed functions , and execute a multi-function instruction, the multi-function instruction comprising an opcode field, the execution comprises responsive to the multi-function instruction for which a query function is specified, execute the query function to determine installed functions available for the instruction multiple functions; executing the query function using the value to determine one or more second installed functions; and executing the query function by storing a result value indicating that one or more of one or more second functions installed are not available in the instruction for multiple functions.
[0011] In one embodiment, the value is defined by a Host Computer hypervisor for a virtual machine of the Host Computer, the virtual machine comprising one or more logical processors, one or more logical processors being assigned to one or more physical processors , a physical processor having one or more second functions installed from the multi-function instruction, wherein the multi-function instruction is performed on the virtual machine by a logical processor of one or more logical processors on a physical processor of one or more physical processors.
[0012] In one embodiment, one or more second functions installed is determined based on the opcode of the multi-function instruction.
[0013] In one embodiment, the hypervisor sets another value by controlling the availability of installed functions for a multi-function instruction running on another virtual machine of the Host Computer system; and executes another instruction of multiple functions on the other virtual machine by another logical processor of one or more other logical processors; responsive to another multi-function instruction specifying another query function, the other query function is performed to determine installed functions available for the other multi-function instruction; the other query function execution uses the other value to determine one or more installed third functions; and the other query function execution stores another result value indicating that one or more of one or more third functions installed are not available for the other multi-function instruction.
[0014] In one embodiment, the stored result value is a significant bit value, where each bit position corresponds to a function, and a bit being 1 indicates that the corresponding function is installed.
[0015] In one embodiment, the query function is specified by a specified function code for multi-function instruction or a specified test bit for multi-function instruction.
[0016] In one embodiment, the multi-function instruction is a zArchitecture instruction consisting of any one of a cryptographic instruction, an Execute Timing Facility Function (PTFF) instruction, a Floating Point Execution Instruction, or an Execute Instruction blocked operation, in which the cryptographic instruction comprises any of an Encrypt message instruction, a Compute Intermediate message instruction, a Compute Digest instruction from the last message, a Compute Digest instruction from the last message, an Instruction from Compute authentication code message, where the multi-function instruction specifies a query function; responsive to the instruction of multiple functions being a cryptographic instruction or a PTFF instruction, the function code specified for instruction of multiple functions to be executed and obtained, the function code obtained consisting of a query function, in which the result value is stored and a plurality of bits, each bit of the plurality of bits indicating whether a corresponding function code is supported; It is responsive to the instruction of multiple functions being a cryptographic instruction or a PTFF instruction, the function code specified for instruction of multiple functions to be executed and obtained, the function code obtained not being the query function, a cryptographic function or a function PTFF and executed according to the obtained function code; It is responsive to the instruction of multiple functions being the instruction to Execute Operation blocked or the instruction to Execute floating point operation and the test bit specified for instruction of multiple functions being 1, a determination is made if a function code specified for instruction of multiple functions are installed, where the result value is stored and a conduit code value; It is responsive to the instruction of multiple functions with the instruction of Execute Operation blocked or the instruction of Execute floating point operation and the test bit specified for instruction of multiple functions being 0, a floating point function or a blocked operation and executed accordingly. with the obtained function code.
[0017] The above as well as additional objectives, characteristics and advantages will become evident in the following written description.
[0018] Other embodiments and aspects are described in detail here and are considered a part of the claimed invention. For a better understanding of the advantages and characteristics, please refer to the description and drawings. BRIEF DESCRIPTION OF THE DRAWINGS
[0019] The embodiments of the invention will now be described, by way of example only, with reference to the accompanying drawings in which: Figure 1A is a diagram showing an example Host computer system; Figure 1B is a diagram showing an example Emulation Host computer system; Figure 1C is a diagram showing an example computer system; Figure 2 is a diagram showing an example computer network; Figure 3 is a diagram showing example elements of a computer system; Figure 4A is a diagram showing an example execution unit; Figure 4B is a diagram showing an example branch unit; Figure 4C is a diagram showing an example Load / Store unit; Figure 5 is a diagram showing an example logical division into portions; Figure 6 is a diagram showing example logical dividing elements; Figure 7 is a diagram showing example logical dividing elements; Figure 8 is a flow showing an example opcode table; Figure 9 is a flow showing an example locking technique; Figure 10 is a flow showing an example locking technique; Figure 11 is a flow showing an example locking technique; and Figures 12-17 show a flow of a function query blocking technique. DETAILED DESCRIPTION
[0020] The embodiments can be put into practice by software (sometimes referred to as Licensed Internal Code, Firmware, Microcodigo, Mili-code, Pico-code and the like, any of which would be compatible with the teaching of the present invention). Referring to Figure 1A, an embodiment of software program code and typically accessed by the processor also known as a CPU (Central Processing Unit) 1 of the system 50 from long-term storage medium 11, as a unit CD-ROM, tape drive, or hard drive. The software program code can be incorporated into any of a variety of known media for use with a data processing system, such as a floppy disk, hard disk drive, or CD-ROM. The code can be distributed on such media, or it can be distributed to users from computer memory 2 or storage of a computer system over a network 10 to other computer systems for use by users of such other systems.
[0021] Alternatively, the program code can be incorporated into memory 2, and accessed by processor 1 using the processor bus. Such program code includes an operating system that controls the function and interaction of the various computer components and one or more application programs. The program code is normally paged from dense storage medium 11 for high speed memory 2 where it is available for processing by processor 1. Techniques and methods for incorporating software program code into memory, in physical media, and / or distributing software code over networks are well known and will not be further discussed here. Program code, when created and stored on a tangible medium (including, however, not limited to electronic memory modules (RAM), flash memory, compact discs (CDs), DVDs, magnetic tape and the like is often mentioned as a “Computer program product.” The average computer program product is typically readable by a processing circuit, preferably on a computer system for execution by the processing circuit.
[0022] Figure 1C illustrates a representative workstation or server hardware system in which embodiments can be put into practice. The system 100 of figure 1C comprises a representative computer system 101, such as a personal computer, a workstation or a server, including optional peripheral devices. Workstation 101 includes one or more processors 106 and a bus employed to connect and enable communication between processor (s) 106 and the other components of system 101 according to known techniques. The bus connects processor 106 to memory 105 and long-term storage 107 which can include a hard drive (including any between magnetic media, CD, DVD and flash memory, for example) or a tape drive, for example. System 101 could also include a user interface adapter, which connects microprocessor 106 across the bus to one or more interface devices, such as a keyboard 104, mouse 103, a Printer / scanner 110 and / or other interface devices, which can be any user interface device, such as a touch sensitive screen, digitized input pad, etc. The bus also connects a display device 102, such as an LCD screen or monitor, to microprocessor 106 through a display adapter.
[0023] System 101 can communicate with other computers or computer networks through a network adapter capable of communicating 108 with a 109 network. Example network adapters are communication channels, token ring, Ethernet or modems. Alternatively, workstation 101 can communicate using a wireless interface, such as a CDPD (cellular digital packet data) card. Workstation 101 can be associated with such other computers on a Local Area Network (LAN) or a Remote Area Network (WAN) or workstation 101 can be a client in a client / server arrangement with another computer , etc. All of these configurations, as well as the appropriate communication hardware and software, are known in the art.
[0024] Figure 2 illustrates a data processing network 200 in which an embodiment can be put into practice. The data processing network 200 may include a plurality of individual networks, such as a wireless network and a wired network, each of which may include a plurality of individual workstations 101 201 202 203 204. Additionally, such as those skilled in With the recognition technique, one or more LANs can be included, where a LAN can comprise a plurality of intelligent workstations coupled to a host processor.
[0025] Still referring to figure 2, networks can also include servers or mainframe computers, such as a gateway computer (client server 206) or application server (remote server 208 that can access a data repository and can also be accessed directly from a workstation 205). A gateway computer 206 serves as an entry point on each network 207. One gateway is required when connecting one networking protocol with another. The gateway 206 can preferably be connected to another network (the internet 207, for example) through a communication link. Gateway 206 can also be directly coupled to one or more workstations 101 201 202 203 204 using a communication link. The gateway computer can be deployed using an IBM eServer ™ zSeries® z9® Server, available from IBM Corp.
[0026] Software programming code is typically accessed by system 106 processor 101 from long-term storage medium 107, such as a CD-ROM drive or hard drive. The software programming code can be incorporated into any of a variety of known media for use with a data processing system, such as a floppy disk, hard drive, or CD-ROM. The code may be distributed on such media, or it may be distributed to users 210 211 from the memory or storage of a computer system over a network to other computer systems for use by users of such other systems .
[0027] Alternatively, programming code 111 can be incorporated into memory 105 and accessed by processor 106 using the processor bus. Such programming code includes as an operating system that controls the function and interaction of the various computer components and one or more application programs 112. Program code is normally paged from dense storage media 107 to high speed memory 105 where it is available for processing by processor 106. Techniques and methods for incorporating software programming code into memory, in physical media and / or distributing software code over networks are well known and will not be further discussed here. Program code, when created and stored on a tangible medium (including, however, not limited to electronic memory modules (RAM), flash memory, compact discs (CDs), DVDs, magnetic tape and the like, is often mentioned as a “Computer program product.” The average computer program product is typically readable by a processing circuit, preferably on a computer system for execution by the processing circuit.
[0028] The cache that is most readily available to the processor (usually faster and smaller than other processor caches) and the lowest cache (L1 or level one) and main storage (main memory) and the highest level cache (L3 if there are 3 levels). The lowest level cache is often divided into an instruction cache (Cache-I) containing machine instructions to be executed and a data cache (Cache-D) containing data operands.
[0029] Referring to Figure 3, an exemplary processor embodiment is shown for processor 106. Typically one or more cache levels 303 are employed for buffer memory blocks to improve processor performance. Cache 303 is a high-speed buffer containing lines of memory data cache that are likely to be used. Typical cache lines are 64, 128 or 256 bytes of memory data. Separate caches are often used for instruction caching rather than data caching. Cache coherence (synchronization of line copies in Memoria and Caches) is often provided by several "Snoop" algorithms well known in the art. The main storage 105 of a processor system is often referred to as a cache. In a processor system having 4 cache levels 303 the main storage 105 is sometimes referred to as the level 5 cache (L5) since it is typically faster and only contains a portion of the non-volatile storage (DASD, Tape, etc.). ) that is available for a computer system. Main storage 105 "caches" pages of Page data in and out of main storage 105 by the operating system.
[0030] A program counter (instruction counter) 311 tracks the address of the current instruction to be executed. A program counter on a z / Architecture and 64-bit processor and can be truncated to 31 or 24 bits to support previous address limits. A program counter is typically incorporated into a PSW (program status word) on a computer so that it persists during context change. In this way, a program in progress, having a program counter value, can be interrupted by, for example, the operating system (changing context from the program environment to the Operating System environment). The program's PSW maintains the program counter value while the program is not active, and the operating system's program counter (on the PSW) is used while the operating system is running. Typically, the Program counter is incremented by an amount equal to the number of bytes in the current instruction. Instructions for RISC (Instruction Set Reduced Computation) are typically of fixed length while instructions for CISC (Instruction Set Complex Instruction) are typically of varying length. IBM z / Architecture instructions are CISC instructions having a length of 2, 4 or 6 bytes. The Program 311 counter is modified by a context change operation or an operation taken from Branch of a Branch instruction, for example. In a context change operation, the current program counter value is saved in a program status word (PSW) along with other status information about the program being executed (such as conduction codes) and a new counter value program is loaded pointing to an instruction for a new program module to be executed. An operation taken from Branching is performed to allow the program to make decisions or loops in the program by loading the result of the Branching Instruction into Program Counter 311.
[0031] Typically, a Search Fetch Unit 305 is employed to fetch instructions on behalf of processor 106. The Fetch Unit searches for “next sequential instructions”, instructions targeted by instructions taken from branching, or first instructions in a program after a change of context. Modern Instruction Search Units often employ prior search techniques to speculatively search for instructions in advance based on the likelihood that previously searched instructions could be used. For example, a search unit can fetch 16 bytes of instruction that includes the next sequential instruction and additional bytes of additional sequential instructions.
[0032] The searched instructions are then executed by processor 106. In one embodiment, the searched instruction (s) are passed to a dispatch unit 306 of the search unit. The dispatch unit decodes the instruction (s) and sends information about the decoded instruction (s) to appropriate units 307 308 310. An execution unit 307 will typically receive information about decoded arithmetic instructions from instruction search unit 305 and perform arithmetic operations on operands according to the instruction's opcode. Operands are provided for execution unit 307 preferably from memory 105, archived records 309 or from an immediate field of the instruction being executed. Execution results, when stored, are stored in memory 105, registers 309 or other machine hardware (such as control registers, PSW registers and the like).
[0033] With reference to figure 5, an example Virtual Machine (VM) environment is shown. A Hypervisor program (which may itself be an Operating System (OS) such as IBM's zVM), running on multiprocessor “Hardware” comprising a plurality of physical processors, a physical main memory and physical adapters to communicate with peripheral I / O devices including storage, networks, displays and the like. The Hypervisor creates VM images (VM1, VM2 and VM3, for example) so that software including an OS and application programs can run on the virtual machine using virtual resources. The software running on a VM is not aware that it is running on a VM, and operates using virtual resources as if they were physical resources. The IBM zVM operating system can create "Host" images, each Host image is effectively a virtual machine. In addition, any zVM host can itself run as OS zVM creating "Second level hosts". In this way, a virtual machine (host image) can be embedded in a hierarchy of virtual machines each zVM playing a hypervisor role for your Host images. On the other hand, a multiprocessor platform can be "physically divided", each physical division can be assigned resources (processors, memory, I / O). Each physical division is a VM since the software running in the division, no it is aware of machine resources not assigned to the division. Thus, the machine's resources are "virtualized". In another embodiment, a host machine can support logical divisions, each logical division is a VM.
[0034] Virtualization is shown, for example, on a white paper from VMware® entitled “Virtualization Overview" and “BMware VMotion and CPU compatibility" VMware® Infrastructure 3 from VMware®. In addition, publication of US patent application no. 2009/0070760 "VIRTUAL MACHINE (VM) MIGRATION BETWEEN PROCESSOR ARCHITECTURES" by Khatri et al., Filed on September 6, 2007 discusses the emulation of a certain set of features to enable a VM migration between similar machine pools by masking selected bits of a CPUID record.
[0035] With reference to figure 6, each VM can have a different OS and different applications. For example, OS1 can be z / OS from IBM and OS2 can be zLinux from IBM, or all OS’s can be the same OS’s as z / OS’s.
[0036] The Hypervisor creates logical characteristics, resources and capacities for each VM based on physical characteristics, resources and capacities. In an example system, portions of physical memory are distributed to each VM through dynamic address translation, physical processors are shared in time between VMs as the I / O capacity.
[0037] With reference to figure 7, each logical processor has access to records of physical characteristics through a Mask of logical characteristics managed by Hypervisor. In this way, software running on logical processors can provide the appearance of operating at a common processor architecture level, even if the actual processors are at different architecture levels. In one example, the Physical Feature record could be an Intel CPUID record that indicates the level of Intel processor architecture as well as specific features that are available to the programmer. The logical feature mask is programmed to provide all or a subset of the physical CPUID processors for the software in a virtual machine (VM) when the VM queries the CPUID of the corresponding Logical processor.
[0038] Intel® x86 processor architecture, “Intel Itanium® Architecture software developer’s manual, volume 2, revision 2.2 January 2006” describes CPUID records to identify features supported by a processor. CPUID records are not privileged and accessed using the indirect mov (de) instruction. All records in addition to the registration CPUID number are reserved and create a reserved Field / Record failure if accessed. Recordings are not allowed and no instructions exist for such an operation. Vendor information is located in CPUID 0 and 1 records and specifies a vendor name, in ASCII, for the processor implementation. All bytes after the end of the string up to the 16th byte are zero. Previous ASCII characters are placed in the lowest numbered register and the lowest numbered byte positions. The CPUID 4 record provides general application level information about processor characteristics. It contains a set of flag bits used to indicate whether a feature is given and supported in the processor model. When a bit and one the characteristic is supported; when 0 the feature is not supported. As new features are added (or removed) from future processor models, the presence (or removal) of new features will be indicated by new feature bits. The CPUID 4 record is logically divided into two halves, which contain both capacity information and general characteristics, but have different usage models and access capabilities; this information reflects the status of any features enabled or disabled. Both the upper and lower halves of the CPUID 4 record are accessible via the move indirect record instruction; depending on the implementation, the latency for this access can be long and this access method is not suitable for low latency code version using auto selection. In addition, the upper half of the CPUID 4 record is also accessible using the test feature instruction; the latency for this access is comparable to that of the test bit instruction and this access method allows low latency code version using auto selection.
[0039] The z / Architecture Operating Principles describe an Extended Storage Facility Lists (STFLE) instruction that as Intel's CPUID record provides software with knowledge of the characteristics (or architecture levels) of Central Processing Units ( Underlying CPUs or processors. The STFLE instruction has the format shown in table 1 below.

[0040] The STFLE instruction (TABLE 1) comprises bits from an Opcode field (0-15), register field B2 (16-19) and an offset field (immediate) D2 (20-31). The execution of the STFLE instruction by a machine, stores a list of bits that provides information about facilities in a program memory location determined by adding the contents of the record specified by field B2 of the instruction to the immediate field D2 of 12 bits, the location of memory starting at the double word (8 bytes, a word has 4 bytes) specified by the address of the second operand ((B2) + D2). The address of the program memory location in zArchicteture is subject to dynamic address translation (DAT).
[0041] Reserved bits are bits that are not currently assigned to represent a facility. For the leftmost double words in which facility bits are assigned, the reserved bits are stored as zeros. Double words to the right of the double word in which the highest numbered feature bit assigned to a model may or may not be stored. Access exclusions and PER events are not recognized for double words that are not stored. The size of the second operand, in double words, is one greater than the value specified in bits 56-63 of the general register 0. The remaining bits of the general register 0 are not assigned and must contain zeros; otherwise, the program may not operate compatible in the future.
[0042] When the size of the second operated is large enough to contain all the feature bits assigned to a model, then the complete feature list is stored in the second operand location, bits 56-63 of the general register 0 are updated to contain less than the number of double words needed to contain all the feature bits assigned to the model, and the conduction code 0 is defined.
[0043] When the size of the second operand is not large enough to contain all the facility bits assigned to a model, then only the number of double words specified by the size of the second operand is stored, bits 56-63 of the register general 0 are updated to contain less than the number of double words needed to contain all the feature bits assigned to the model, and condition code 3 is defined.
[0044] The execution of the instruction results in the definition of a value of the Conduction Code, the value of the Conduction Code and saved during context change with the Program Status Word (PSW). Special conditions:
[0045] The second operand must be designated in a double word limit; otherwise, a specification exception is recognized.
[0046] Resulting conduit code: 0 complete feature list stored 1 2 3 Incomplete feature list stored
[0047] Program exclusions:. access (store, second operand). operation (if the facility to store extended facility list is not installed). Specification
[0048] Programming notes:
[0049] The execution of STORE ESETNDIDA FACILIDADE LIST can be significantly slower than that of simply testing a byte in storage. Programs that often need to test for the presence of a feature - for example, dual path code in which the feature is used on one route, but not on another - must execute the STORE EXTENDED FACILITY LIST instruction once during initialization. Subsequently, the program can test the presence of the facility in relation to examining the stored result, using an instruction such as MASK TEST.
[0050] When condition code 0 is set, bits 56-63 of general register 0 are updated to indicate the number of double words stored. If the program chooses to ignore the results in the general register 0, then it must ensure that the second operand in storage is set to zero before executing STORE EXTENDED FACILITY LIST.
[0051] Table 2 shows STFLE bits assigned to z / Architecture of the state of the art and their meaning. A bit is set to one regardless of the current architectural mode if its meaning is true. A meaning applies to the current architectural mode unless it is said to apply to a specific architectural mode.
[0052] Unassigned bits are reserved to indicate new facilities; these bits can be stored as ones in the future.
[0053] The state of the art z / Architecture facility list is defined as shown in Table 2 below: Table 2 Meaning of bit-when-bit-and-one: 0 the instructions marked “N3” in the summary figures of instructions in Chapters 7 and 10 of z / Architecture are installed. 1 z / Architecture architectural mode is installed. 2 The z / Architecture and active architectural mode. When this bit is zero, the architectural mode ESA / 390 is active. 3 The DAT enhancement facility is installed in z / Architecture architectural mode. The improved DAT facility includes the instructions INVALID DAT TABLE ENTRY (DTE) and COMPARE AND CHANGE AND PURGE (CSPG). 4 INVALID DAT TABLE ENTRY (IDTE) performs the invalidation and release operation by selectively releasing combined region and segment table entries when an segment table entry or entries are invalidated. IDTE also performs the ASCE release-operation. Unless bit 4 is one, IDTE simply purges all TLBs. Bit 3 is one if bit 4 is one. 5 INVALID DAT TABLE ENTRY (IDTE) performs the invalidation and release operation by selectively releasing combined region and segment table entries when an region table entry or entries are invalidated. Bits 3 and 4 are one if bit 5 is one. 6 The ASN-e-LX reuse facility is installed in z-Architecture architectural mode. 7 The facility to store the extended and installed facility list. 8 The enhanced DAT facility and installed in z-Architecture architectural mode. 9 The ease of perceiving running status and installed in z-Architecture architectural mode. 10 The SSKE facility conditional and installed in z-Architecture architectural mode. 11 The configuration topology facility is installed in z-Architecture architectural mode. 16 The extended installation facility 2 is installed. 17 The message security aid is installed. 18 The long travel facility and installed in z-Architecture architectural mode. 19 The long travel facility has high performance. Bit 18 is one if bit 19 is one. 20 The HFP-multiply and add / subtract and installed facility. 21 The immediate facility extended and installed in z-Architecture architectural mode. 22 The extended translation facility 3 is installed in the z-Architecture architectural mode. 23 The non-standard HFP extension facility is installed in z-Architecture architectural mode. 24 The ETF2 enhancement facility is installed. 25 The facility to store watch quickly and installed in z-Architecture architectural mode. 26 The analysis improvement facility is installed in the z-Architecture architectural mode. 27 The facility to move with optional specifications is installed in z-Architecture architectural mode. 28 The TOD-clock steering facility is installed in z-Architecture architectural mode. 30 The ETF3 enhancement facility and installed in z-Architecture architectural mode. 31 The ease of extracting-CPU-time and installed in z-Architecture architectural mode. 32 The facility to compare-and-exchange-and-store and installed in z-Architecture architectural mode. 33 The compare-and-exchange-and-store facility 2 is installed in z-Architecture architectural mode. 34 The general instructions extension facility is installed in the z-Architecture architectural mode. 35 The ease of executing extensions is installed in the z-Architecture architectural mode. 39 Attributed to internal IBM use. 41 The floating point support enhancement facilities (transfer-GR-FPR, signal-handling-FPS and DFP rounding) are installed in the z-Architecture architectural mode. 42 The DFP (decimal floating point) facility is installed in z-Architecture architectural mode. 43 The DFP (decimal floating point) feature has high performance. Bit 42 is one if bit 43 is one. 44 The PFPO instruction is installed in the z-Architecture architectural mode.
[0054] An instruction can perform a unique function in an architecture or, in some cases, any of a plurality of selectable functions. The selectable functions defined for an instruction may differ from machine to machine. For example, a multi-function instruction, when first introduced in a set of architected instructions, may have only a few selectable functions. A set of later archived instructions can introduce more selectable functions to the instruction of multiple functions previously introduced. In one embodiment, a VM can be assigned a subset of the selectable function of the physical processor so an instruction, running on a VM logical processor can consult a list of available functions of the logical processor and only the functions assigned to the VM are returned, although the physical processor can perform more selectable functions. In one embodiment, this is done through a Function Indication Instruction Interception Facility (FIIIF) that enables a hypervisor to arrest or intercept a host's execution of this query function (virtual machine), to present the reduced list of functions available. In another embodiment, the hypervisor specifies, for example, using a bit mask, the set of functions to be reported to the host, and the query function of the instruction for multiple functions reports this list. In addition, in one embodiment, an instruction, executing on the logical processor, will experience a program exception if it tries to execute a selected selectable function.
[0055] In the case of a multi-function instruction capable of consulting the existence of installed functions and also of executing a selected function of the installed functions, the execution of the installed functions including the query function can be performed in hardware (including circuit and micro-code) , for example) for best performance. In one embodiment, when the FIIIF feature is installed, the query function is intercepted by software for execution rather than hardware. In this way, only the execution of the query function will encounter additional delay to determine which installed features to report. In one embodiment, the interception is for the Hypervisor code that performs the query function and returns appropriate results on behalf of the virtual machine.
[0056] An example of an instruction having selectable functions, and the instruction CODE MESSAGE from z / Architecture.
[0057] The ENCRYPTION MESSAGE (KM) instruction can perform any of a plurality of message encryption functions. One of the functions provided by ENCRYPTION MESSAGE is to consult the processor in relation to a significant list of message encryption functions supported by the processor.
[0058] The format of the instruction CIFRAR MESSAGE (TABLE 3) is as follows, where R1 designates a first General Register, and R2 designates a second General Register.

[0059] The execution of the instruction CIFRAR MENASGEM (TABLE 3) is as follows:
[0060] A function specified by the function code in general implicit register 0 is performed.
[0061] Bits 16-23 of the instruction are ignored.
[0062] The bit positions 57-63 of the general register 0 contain the function code.
[0063] The function codes currently assigned to ENCRYPTION MESSAGE and ENCRYPTION MESSAGE WITH CHAIN, respectively (0-3 and 18-20) are shown in Table 4. All other function codes are not assigned. For encryption functions, bit 56 is the modifying bit that specifies whether an encryption operation or decryption should be performed. The modifying bit is ignored for all other functions. All other bits in the general register 0 are ignored.
[0064] The implicit general register 1 contains the logical address of the leftmost byte of the parameter block in storage. In the 24-bit addressing mode, the content of bit positions 40-63 of general register 1 constitutes the address, and the content of bit positions 039 is ignored. In the 31-bit addressing mode, the contents of bit positions 33-63 of general register 1 constitute the address, and the contents of bit positions 0-32 are ignored. In 64-bit addressing mode, the contents of bit positions 0-63 of general register 1 constitute the address.
[0065] The query function provides the means of indicating the availability of other functions. The contents of general records specified by instruction fields (R1, R2) and R2 + 1 are ignored for the query function.
[0066] For all other functions, the second operand (specified by R2) is encrypted as specified by the function code using a cryptographic key in the parameter block, and the result is placed at the location of the first operand.
[0067] To ENCRYP MESSAGE WITH CHAIN, encryption also uses an initial chaining value in the parameter block, and the chaining value is updated as part of the operation. The use of the registry for 24-bit addressing is shown in table 5.
[0068] Field R1 designates a general record and must designate an even numbered record, otherwise a specification exception is recognized.
[0069] Field R2 designates an odd-numbered pair of general records and must designate an even-numbered record; otherwise, a specification exception is recognized.
[0070] The location of the leftmost byte of the first and second operands is specified by the contents of the general registers R1 and R2, respectively. The number of bytes at the location of the second operand is specified in the general register R2 + 1. The first operand is the same length as the second operand.
[0071] As part of the operation, the addresses in the general registers R1 and R2 are increased by the number of bytes processed, and the length in the general register R2 + 1 is decreased by the same number. The formation and updating of addresses and length is dependent on the addressing mode.
[0072] In the 24-bit addressing mode, the contents of bit positions 40-63 of the general registers R1 and R2 constitute the addresses of the first and second operands, respectively, and the contents of bit positions 0-39 are ignored; bits 40-63 of the updated addresses replace the corresponding bits in the general registers R1 and R2, transports from the bit position 40 of the updated address are ignored, and the contents of bit positions 32-39 of the general registers R1 and R2 are set in zeros. In the 32-bit addressing mode, the contents of bit positions 33-63 of the general registers R1 and R2 constitute the addresses of the first and second operands, respectively, and the contents of bit positions 0-32 are ignored; bits 33-63 of the updated addresses replace the corresponding bits in the general registers R1 and R2, transports from the bit position 33 of the updated address are ignored, and the content of bit position 32 of the general registers R1 and R2 is defined in zero. In 64-bit addressing mode, the contents of bit positions 0-63 of the general registers R1 and R2 constitute the addresses of the first and second operands, respectively; bits 0-63 of the updated addresses replace the contents of the general registers R1 and R2 and transports from bit position 0 are ignored.
[0073] In both 24-bit and 31-bit addressing modes, the contents of bit positions 32-63 in the general register R2 +1 form a 32-bit unsigned binary integer that specifies the number of bytes in the first and in the according to operands, and the contents of bit positions 0-31 are ignored; bits 32-63 of the updated value replace the corresponding bits in general register R2 + 1. In 64-bit addressing mode, the contents of bit positions 0-63 in general register R2 + 1 form a 64-bit unsigned binary integer which specifies the number of bytes in the first and second operands; and the updated value replaces the contents of the general register R2 + 1.
[0074] In 24-bit or 31-bit addressing mode, the contents of bit positions 0-31 of the general registers R1, R2 and R2 + 1, always remain unchanged. The figure below shows the contents of the general records just described.
[0075] In the access register mode, access registers 1, R2 and R2 specify the address spaces containing the parameter block, first and second operands, respectively.
[0076] The result is obtained as if processing started at the left end of both the first and second operands and proceeds to the right, block by block. The operation ends when the number of bytes in the second operand as specified in the general register R2 + 1 has been processed and placed at the location of the first operand (called the normal conclusion) or when a number determined by CPU of blocks that is less than the length of the second operand has been processed (called partial completion). The number of blocks determined per CPU depends on the model, and can be a different number each time the instruction is executed. The number of blocks determined by the CPU is normally not zero. In certain unusual situations, this number can be zero, and condition code 3 can be set without progress. However, the CPU protects against an endless recurrence of this case without progress.
[0077] The results in the first operand location and the chaining value field are unpredictable if any of the following situations occur: The cryptographic key field overlaps any portion of the first operand. The chaining value field overlaps any portion of the first operand or second operand. The first and second operands overlap destructively. Operands are said to destructively overlap when the location of the first operand would be used as a source after the data has been moved into it, assuming that processing must be performed from left to right and one byte at a time.
[0078] When the operation ends due to normal completion, the conduction code 0 is defined and the resulting value in R2 + 1 and zero. When the operation ends due to partial completion, conduction code 3 is defined and the resulting value in R2 + 1 is not zero.
[0079] When a storage change PER event is recognized, a number less than 4K additional bytes is stored in the first operating locations before the event is reported.
[0080] When the length of second operand is initially zero, the parameter block, first and second operands are not accessed, general registers R1, R2 and R2 +1 are not changed, and the conduction code 0 is defined.
[0081] When the contents of fields R1 and R2 are the same, the contents of the designated records are increased only by the number of bytes processed, not twice the number of bytes processed.
[0082] As noted by other CPUs and channel programs, references to the parameter block and storage operands can be multiple access references, accesses to these storage locations are not necessarily simultaneous to the block, and the sequence of these accesses or references and indefinite.
[0083] In certain unusual situations, the execution of instruction can be completed by defining condition code 3 without updating the registers and chaining value to reflect the last unit of the first and second operands processed. The size of the unit processed in this case depends on the situation and the model, however it is limited so that the portion of the first and second operands that were processed and not reported do not overlap in storage. In all cases, change bits are set and PER storage change events are reported, when applicable, for all processed first operand locations.
[0084] Access exclusions can be reported for a larger portion of an operand than is processed in a single execution of the instruction; however, access exclusions are not recognized for locations beyond the length of an operand or for locations larger than 4K bytes beyond the current location being processed.
[0085] The function codes for ENCRYPTION MESSAGE are as follows


[0086] Using the CODE MESSAGE instruction as an example, an example machine can implement Cipher MESSAGE functions. In the example implementation, Host processors can implement all of the functions shown (function code 0-3 and 18-20). A host operating system (OS) (or hypervisor) can create one or more virtual machines for host OSs. A virtual machine can be defined for a previous level architecture, without the instructions of Cipher Message.
[0087] According to one embodiment, if an Instruction Lock Facility were installed and Cipher MESSAGE instructions were designated as Blocked instructions for a VM, the virtual machine would not allow the execution of the CYCLE MESSAGE instruction by programs running on the virtual machine, although the underlying Host machine would support Cipher MESSAGE instructions, an attempt to execute a Cipher MESSAGE instruction on the VM would result in a program check (program exclusion).
[0088] According to another embodiment, if a function blocking facility were installed and only a subset of the CYCLE MESSAGE functions (function codes 0-3 for example) were allowed on a VM, the virtual machine would allow CIFRAR execution MESSAGE, however, it would not allow the execution of an encrypted instruction MESSAGE of an encrypted message having a function code other than 0-3 by programs running on the virtual machine, although the underlying host machine supported instructions for encrypting messages by supporting the function codes (0 -3 and 18-20). An attempt to execute an ENCRYPTION MESSAGE instruction having function codes other than 0-3 like any 18-20) would result in a program check (program exclusion).
[0089] In another embodiment, if a Fungao query / test facility were installed and only a subset of the CIFRAR MENASGEM functions (function codes 0-3, for example) were allowed on a VM, the execution of a query for ENCRYPTION MESSAGE from the functions ENCRYPTION MESSAGE would only return function codes 0-3, although the underlying Host machine supported function codes 0-3 and 1820.
[0090] ANOTHER EXAMPLE INSTRUCTIONS FOR MULTIPLE FUNCTIONS OF zArchitecture: INSTRUCTIONS FOR COMPUTING DIGEST OF INTERMEDIARY MESSAGE (KIMD) and COMPUTING DIGEST OF ULTIMA MENASGEM (KLMD):
[0091] When executed by a computer system, a function specified by the function code in the general register 0 is performed. Bits 16-23 of the instruction and the R1 field are ignored. Bit positions 57-63 of general register 0 contain the function code. Bit 56 of general register 0 must be zero; otherwise, a specification exception is recognized. All other bits in the general register 0 are ignored. The general register 1 contains the logical address of the leftmost byte of the parameter block in storage. In the 24-bit addressing mode, the contents of bit positions 40-63 of the general register 1 constitute the address, and the contents of bit positions 039 are ignored. In the 31-bit addressing mode, the bit position contents 33-63 of the general register 1 constitute the address and the bit position contents 032 are ignored. In 64-bit addressing mode, the contents of bit positions 0-63 of general register 1 constitute the address. All other function codes are not assigned. The query function provides the means to include the availability of the other functions. The contents of general registers R2 and R2 + 1 are ignored for the query function. For all other functions, the second operand is processed as specified by the function code using an initial chaining value in the parameter block, and the result replaces the chaining value. To COMPUTATE LAST MESSAGE DIGEST, the operation also uses a message bit length in the parameter block. The operation continues until the end of the second operand location is reached or a determined number of bytes CPU has been processed, whichever comes first. The result is indicated in the conduction code. The R2 field designates an odd-numbered pair of general records and must designate an even-numbered record; otherwise, a specification exception is recognized. The location of the left most byte of the second operand is specified by the contents of the general register R2. The number of bytes in the second operand location is specified in the general register R2 + 1. As part of the operation, the address in the general register R2 is increased by the number of bytes processed from the second operand, and the length in the general register R2 +. 1 and decreased by the same number. The formation and updating of the address and length depends on the addressing mode. In the 24-bit addressing mode, the contents of bit positions 40-63 of the general register R2 constitute the address of the second operand, and the contents of bit positions 0-39 are ignored; bits 40-63 of the updated address replace the corresponding bits in the general register R2, transports from the bit position 40 of the updated address are ignored, and the contents of bit positions 32-39 of the general register R2 are set to zeroes. In the 31-bit addressing mode, the contents of bit positions 33-63 of the general register R2 constitute the address of the second operand, and the contents of its 0-32 positions are ignored; bits 33-63 of the updated address replace the corresponding bits in the general register R2, transports from the bit position 33 of the updated address are ignored, and the bit position content 32 of the general register R2 is set to zero. In 64-bit addressing mode, the contents of bit positions 0-63 in the general register R2 constitute the address of the second operand; bits 0-63 of the updated address replace the contents of general register R2 and transports from bit position 0 are ignored. In 24-bit and 31-bit addressing modes, the contents of bit positions 32-63 in the general register R2 + 1 form a 32-bit unsigned binary integer that specifies the number of bytes in the second operand; and the updated value replaces the contents of bit positions 32-63 of the general register R2 + 1. In the 64-bit addressing mode, the contents of bit positions 0-63 of the general register R2 + 1 form an unsigned binary integer 64-bit specifying the number of bytes in the second operand; and the updated value replaces the contents of the general register R2 + 1. In the 24-bit or 31-bit addressing mode, the contents of bit positions 0-31 of the general registers R2 and R2 + 1, always remain unchanged. In the access register mode, access registers 1 and R2 specify the address spaces containing the parameter block and second operands, respectively. The result is obtained as if processing starts at the left end of the second operands and proceeds to the right, block by block. The operation ends when all the source bytes in the second operand have been processed (called the normal completion) or when a number determined per CPU of blocks that is less than the length of the second operand has been processed (called the partial completion). The number of blocks determined per CPU depends on the model, and can be a different number each time the instruction is executed. The number of blocks determined by the CPU is normally not zero. In certain unusual situations, this number can be zero, and condition code 3 can be set without progress. However, the CPU protects against an endless recurrence of this case without progress. When the chaining value field overlaps any portion of the second operand, the result in the chaining value field is unpredictable. For COMPUTING INTERMEDIATE MESSAGE DIGEST, normal conclusion occurs when the number of bytes in the second operating as specified in the general register R2 + 1 has been processed. To COMPUTATE LAST MESSAGE DIGEST, after all the bytes in the second operating as specified in the general register R2 + 1 have been processed, the filling operation is performed and then the normal completion occurs. When the operation ends due to normal completion, the conduction code 0 is set and the resulting value in R2 + 1 is zero. When the operation ends due to partial completion, conduction code 3 is defined and the resulting value in R2 + 1 is not zero. When the length of the second operand is initially zero, the second operand is not accessed, general registers R2 and R2 + 1 are not changed, and condition code 0 is defined. To COMPUTATE INTERMEDIARY MESSAGE DIGEST, the parameter block is not accessed. However, to COMPUTATE LAST MESSAGE DIGEST, the filling operation of the empty block case (L = 0) is performed and the result is stored in the parameter block. As noted by other CPUs and channel programs, references to the parameter block and storage operands can be multiple access references, accesses to these storage locations are not necessarily simultaneous to the block, and the sequence of these accesses or references is undefined. Access exclusions can be reported for a larger portion of the second operand than is processed in a single execution of the instruction; however, access exclusions are not recognized for locations beyond the length of the second operand or for locations more than 4K bytes beyond the current location being processed. Query-KIMD (Function code KIMD 0)
[0092] A 128-bit status word is stored in the parameter block. The bits 0-127 of this field correspond to the function codes 0-127, respectively, of the instruction COMPUTAR DIGESTO DE MESSAGEM INTERMEDIARY. When a bit is one, the corresponding function is installed; otherwise, the function is not installed. Condition code 0 is defined when the execution of the KIMD Query function is completed, • condition code 3 is not applicable in that function. KIMD-SHA-1 (Function code KIMD 1)
[0093] An intermediate message digest of 20 bytes is generated for the 64-byte message blocks in operand 2 using the SHA-1 block digest algorithm with a 20-byte chaining value in the parameter block. The generated intermediate message digest, also called the output chaining value (OCV), is stored in the chaining value field of the parameter block. KIMD-SHA-256 (Function code KIMD 2)
[0094] An intermediate message digest of 32 bytes is generated for the message blocks of 64 bytes in operand 2 using the block digest algorithm SHA-256 with the chain value of 32 bytes in the parameter block. The generated intermediate message digest, also called the output chaining value (OCV), is stored in the chaining value field of the parameter block. KIMD-SHA-512 (Function code KIMD 3)
[0095] An intermediate message digest of 64 bytes is generated for the message blocks of 128 bytes in operand 2 using the block digest algorithm SHA-512 with the chaining value of 64 bytes in the parameter block. The generated intermediate message digest, also called the output chaining value (OCV), is stored in the chaining value field of the parameter block. KLMD-Query (Function code KLMD 0)
[0096] A 128-bit status word is stored in the parameter block. Bits 0-127 of this field correspond to function codes 0-127, respectively of the instruction COMPUTAR DIGESTO DE ULTIMA MESSAGE. When a bit is one, the corresponding function is installed; otherwise, the function is not installed. Condition code 0 is defined when executing the Query KLMD function and is completed, • condition code 3 is not applicable for this function. KLMD-SHA-1 (Function code KLMD 1)
[0097] The message digest for message (M) in operand 2 is generated using the SHA-1 algorithm with the message bit length chaining value and information in the parameter block. If the length of the message in operand 2 is equal to or greater than 64 bytes, an intermediate message digest is generated for each 64-byte message block using the SHA-1 block digest algorithm with a 20 byte chaining value in the parameter block, and the intermediate message digest generated, also called the output chaining value (OCV), is stored in the chaining value field of the parameter block. This operation is repeated until the remaining message is less than 64 bytes. If the length of the message or the remaining message is zero bytes, then the operation is performed. If the length of the message or the remaining message is between one byte and 55 bytes inclusive, then the operation is performed; if the length is between 56 bytes and 63 bytes inclusive, then the operation is performed. The message digest, also called the output chaining value (OCV), is stored in the chaining value field of the parameter block. KLMD-SHA-256 (Function code KLMD 2)
[0098] The message digest for message (M) in operand 2 is generated using the SHA-256 algorithm with the message bit length chaining value and information in the parameter block. If the message in operand 2 is equal to or greater than 64 bytes, an intermediate message digest is generated for each 64-byte message block using the SHA-256 block digest algorithm with the 32-byte chaining value in the parameter, and the intermediate message digest generated, also called the output chaining value (OCV), is stored in the chaining value field of the parameter block. This operation is repeated until the remaining message is less than 64 bytes. If the length of the message or the remaining message is zero bytes, then the operation is performed. If the length of the message or the remaining message is between one byte and 55 bytes inclusive, then the operation is performed; if the length is between 56 bytes and 63 bytes inclusive, then the operation is performed. The message digest, also called the output chaining value (OCV), is stored in the chaining value field of the parameter block. KLMD-SHA-512 (Function code of KLMD 3)
[0099] The message digest for message (M) in operand 2 is generated using the SHA-512 algorithm with the message bit length chaining value and information in the parameter block. If the message in operand 2 is equal to or greater than 128 bytes, an intermediate message digest is generated for each 128-byte message block using the SHA-518 block digest algorithm with a 64-byte chaining value in the parameter, and the intermediate message digest generated, also called the output chaining value (OCV), is stored in the chaining value field of the parameter block. This operation is repeated until the remaining message is less than 128 bytes. If the length of the message or the remaining message is zero bytes, then the operation is performed. If the length of the message or the remaining message is between one byte and 111 bytes inclusive, then the operation is performed; if the length is between 112 bytes and 127 bytes inclusive, then the operation is performed. The message digest, also called the output chaining value (OCV), is stored in the chaining value field of the parameter block. INSTRUCTIONS FOR COMPUTING MESSAGE AUTHENTICATION CODE (KMAC)
[0100] When performed by a computer system, a function specified by the function code in general register 0 is performed. Bits 16-23 of the instruction and the R1 field are ignored. Bit positions 57-63 of the general register 0 contain the function code. All other function codes are not assigned. Bit 56 of general register 0 must be zero; otherwise, a specification exception is recognized. All other bits in the general register 0 are ignored. The general register 1 contains the logical address of the leftmost byte of the parameter block in storage. In the 24-bit addressing mode, the contents of bit positions 40-63 of the general register 1 constitute the address, and the contents of bit positions 0-39 are ignored. In the 31-bit addressing mode, the contents of bit positions 33-63 of the general register 1 constitute the address, and the contents of bit positions 0-32 are ignored. In 64-bit addressing mode, the contents of bit positions 063 in general register 1 constitute the address. The query function provides the means of indicating the availability of the other functions. The contents of general registers R2 and R2 + 1 are ignored. For all other functions, the second operand is processed as specified by the function code using an initial chaining value in the parameter block and the result replaces the chaining value. The operation also uses an encryption key in the parameter block. The operation continues until the end of the second operand location is reached or a number of bytes determined per CPU has been processed, whichever comes first. The result is indicated in the conduction code. The R2 field designates an odd-numbered pair of general records and must designate an even-numbered record; otherwise, a specification exception is recognized. The location of the left most byte of the second operand is specified by the contents of the general register R2. The number of bytes in the second operand location is specified in the general register R2 + 1. As part of the operation, the address in the general register R2 is increased by the number of bytes processed from the second operand, and the length in the general register R2 +. 1 and decreased by the same number. The formation and updating of the address and length depends on the addressing mode. In the 24-bit addressing mode, the contents of bit positions 40-63 of the general register R2 constitute the address of the second operand, and the contents of bit positions 0-39 are ignored; bits 40-63 of the updated address replace the corresponding bits in the general register R2, transports from the bit position 40 of the updated address are ignored and the contents of bit positions 32-39 of the general register R2 are set to zeroes. In the 31-bit addressing mode, the contents of bit positions 33-63 of the general register R2 constitute the address of the second operand, and the contents of bit positions 0-32 are ignored; bits 33-63 of the updated address replace the corresponding bits in the general register R2, transports from the bit position 33 of the updated address are ignored and the contents of bit position 32 of the general register R2 are set to zero. In 64-bit addressing mode, the contents of bit positions 0-63 in the general register R2 constitute the address of the second operand; bits 0-63 of the updated address replace the contents of the general register R2 and transports from bit position 0 are ignored. In both 24-bit and 31-bit addressing modes, the contents of bit positions 32-63 in the general register R2 + 1 form a 32-bit unsigned binary integer that specifies the number of bytes in the second operand; and the updated value replaces the contents of bit positions 32-63 of the general register R2 + 1. In the 64-bit addressing mode, the contents of bit positions 0-63 of the general register R2 + 1 form an unsigned binary integer 64-bit specifying the number of bytes in the second operand; and the updated value replaces the contents of the general register R2 + 1. In the 24-bit or 31-bit addressing mode, the contents of bit positions 0-31 of the general registers R2 and R2 + 1, always remain unchanged. In register access mode, access registers 1 and R2 specify the address spaces containing the parameter block and second operand, respectively. The result is obtained as if the processing starts at the left end of the second operand and proceeds to the right, block by block. The operation ends when all the source bytes in the second operand have been processed (called the normal completion) or when a number of blocks determined by the CPU that is less than the length of the second operand has been processed (called the partial completion). The number of blocks determined by the CPU depends on the model, and can be a different number each time the instruction is executed. The number of blocks determined by the CPU is normally not zero. In certain unusual situations, this number can be zero and condition code 3 can be set without progress. However, the CPU protects against an endless recurrence of this case without progress. When the chaining value field overlaps any portion of the second operand, the result in the chaining value field is unpredictable. Normal completion occurs when the number of bytes in the second operating as specified in the general register R2 + 1 has been processed. When the operation ends due to normal completion, the conduction code 0 is set and the resulting value in R2 + 1 is zero. When the operation ends due to partial completion, conduction code 3 is defined and the resulting value in R2 + 1 is not zero. When the length of the second operand is initially zero, the second operand and the parameter block are not accessed, general registers R2 and R2 + 1 are not changed and condition code 0 is defined. As noted by other CPUs and channel programs, references to the parameter block and storage operands can be multiple access references, accesses to these storage locations are not necessarily simultaneous in block, and the sequence of these accesses or references is undefined. Access exclusions can be reported for a larger portion of the second operand than is processed in a single execution of the instruction; however, access exclusions are not recognized for locations beyond the length of the second operand or for locations more than 4K bytes beyond the current location being processed. KMAC consultation (Function code 0)
[0101] A 128-bit status word is stored in the parameter block. Bits 0-127 of this field correspond to function codes 0-127, respectively, of the KMAC instruction. When a bit is one, the corresponding function is installed; otherwise, the function is not installed. Condition code 0 is defined when the execution of the KMAC query function is completed, • condition code 3 is not applicable to that function. KMAC-DEA (Function code 1)
[0102] The message authentication code for the 8-byte message blocks (M1, M2, ..., Mn) in operand 2 is computed using the DEA algorithm with the 64-bit encryption key and the chaining value 64 bits in the parameter block. The message authentication code, also called the output chaining value (OCV), is stored in the chaining value field of the parameter block. KMAC-TDEA-128 (function code 2)
[0103] The message authentication code for the 8-byte message blocks (M1, M2, ..., Mn) in operand 2 is computed using the TDEA algorithm with the two 64-bit cryptographic keys and the value of 64-bit chaining in the parameter block. The message authentication code, also called the output chaining value (OCV), is stored in the chaining value field of the parameter block. KMAC-TDEA-192 (Function code 3)
[0104] The message authentication code for the 8-byte message blocks (M1, M2, ..., Mn) in operand 2 is computed using the TDEA algorithm with the two 64-bit cryptographic keys and the value of 64-bit chaining in the parameter block. The message authentication code, also called the output chaining value (OCV), is stored in the chaining value field of the parameter block. INSTRUCTION TO PERFORM LOCKED OPERATION
[0105] When executed by a computer system, after the lock specified in general register 1 has been obtained, the operation specified by the function code in general register 0 is performed and then the lock is released. However, as noted by other CPUs: (1) storage operands, including fields in a list of parameters that can be used, can be searched for and can be tested for store access exclusions if storage in a tested location is possible , before the lock is obtained, and (2) operands can be stored in the parameter list after the lock has been released. If an operand not in the parameter list is fetched before the lock is obtained, it is fetched again after the lock has been obtained. The function code can specify any of six operations: compare and load, compare and exchange, compare double and exchange, compare and exchange and store, compare and exchange and store double or compare and exchange and store triple. A test bit in the general register 0 specifies, when one, that a lock must not be obtained and none of the six operations must be performed, however, instead, the validity of the function code must be tested. This will be useful if additional function codes for additional operations are assigned in the future. This definition is written as if the test bit was zero except when mentioned otherwise. If compare and load is specified, the comparison value of the first operand and the second operand are compared. If they are the same, the fourth operating and placed at the third operating location. If the comparison indicates inequality, the second operand is placed in the first operand comparison value location as a new first operand comparison value. If compare and exchange is specified, the comparison value of the first operand and the second operand are compared. If they are the same, the replacement value for the first operand is stored at the location of the second operand. If the comparison indicates inequality, the second operand is placed in the first operand comparison value location as a new first operand comparison value. If double compare and switch is specified, the comparison value of the first operand and the second operand are compared. If they are the same, the comparison value of the third operand and the fourth operand are compared. If the two comparisons indicate equality, the substitution values for first operand and third operand are stored at the second operand and fourth operand location, respectively. If the first comparison indicates inequality, the second operand is placed in the first operand comparison value location as a new first operand comparison value. If the first comparison indicates equality, but the second does not, the fourth operating is placed in the third-party comparison value location as a new third-party comparison value. If comparing and exchanging and storing, storing double, or storing triple is specified, the comparison value of the first operand and the second operand are compared. If they are the same, the replacement value of the first operand is stored at the location of the second operand, and the third operand is stored at the location of the fourth operand. Then, if the operation is the double store or triple store operation, the fifth operand is stored as the sixth operand location and, if it is the triple store operation, the seventh operand is stored at the eighth operand location. If the comparison of first operand indicates inequality, the second operand is placed in the first operand comparison value location as a new first operand comparison value. After any of the six operations, the result of the comparison or comparisons is indicated in the conduction code. The function code (FC) is in bit positions 56-63 of the general register 0. The function code specifies not only the operation to be performed, but also the length of the operands and whether the comparison and replacement values of the first operand and the third operand or the comparison and substitution values of the third operand, which are referred to collectively simply as the first and third operands, are in general records or a list of parameters. The default of the function codes is as follows: * A function code that is multiple of 4 (including 0) specifies a length of 32 bits with the first and third operands in bit positions 32-63 of the general registers. * A function code that is more than a multiple of 4 specifies a length of 64 bits with the first and third operands in a list of parameters. * A function code that is 2 more than a multiple of 4 specifies a length of 64 bits with the first and third operands in bit positions 0-63 of the general registers. * A function code that is 3 more than a multiple of 4 specifies a length of 128 bits with the first and third operands in a list of parameters.
[0106] For example, PLO.DCS can be used to mean EXECUTE BLOCKED OPERATION with function code 8. In the letters, the letter “G” indicates an operand length of 64 bits, the letter “R” indicates that some or all 64-bit operands are in general registers, and the letter "X" indicates an operand length of 128 bits. Function codes that have not been assigned to operations or that specify operations that the CPU cannot perform because operations are not implemented (installed) are called invalid. Bit 55 of general register 0 and test bit (T). When bit 55 is zero, the function code in the general register 0 must be valid; otherwise, a specification exception is recognized. When bit 55 is one, the conduction code is set to 0 if the function code is valid or 3 if the function code is invalid, and no other operation is performed. Bits 32-54 of general register 0 must all be zeros; otherwise, a specification exception is recognized. When bit 55 of the register is one, this is the only exception that can be recognized. Bits 0-31 of the general register 0 are ignored. The lock to be used is represented by a program lock token (PLT) whose logical address is specified in the general register 1. In the 24-bit addressing mode, the PLT address and bits 40-63 of the general register 1, and bits 0-39 of the record are ignored. In 31-bit addressing mode, the PLT address and bits 3363 of the register, and bits 0-32 of the register are ignored. In 64-bit addressing mode, the address PLT and bits 063 of the register. For even-numbered function codes, including 0, the comparison value of first operand is in the general register R1. For even number function codes starting with 4, the replacement value of first operand is in the general register R1 + 1, and R1 designates an odd-numbered pair of records and must designate an even-numbered record; otherwise, a specification exception is recognized. For function codes 0 and 2, R1 can be even or odd. For function codes 0, 2, 12 and 14, the third operand is in the general register R3, and R3 can be even or odd. For function codes 8 and 10, the comparison value of the third operand is in the general register R3, the replacement value of the third operand is in the general register R3 + 1, and R3 designates an odd pair of records and must designate an even number record; otherwise, a specification exception is recognized. For all function codes, fields B2 and D2 of the instruction specify the second operand address. For function codes 0, 2, 8, 10, 12 and 14, fields B4 and D4 of the instruction specify the fourth operating address. For function codes 1, 3, 5, 7, 9, 11, 13, 15 and 16-23, fields B4 and D4 of the instruction specify the address of a list of parameters that is used by the instruction, and that address is not called the operating room address. The parameter list contains odd-numbered operands, including comparison and substitution values, and addresses of even-numbered operands other than the second operand. In the access register mode, the parameter list also contains access list entry tokens (ALETs) associated with the even number operand addresses. In the access record mode, for function codes that cause the use of a parameter list containing an ALET, R3 must not be zero; otherwise, a specification exception is recognized. Operand addresses in a parameter list, if used, are in double words in the list. In 24-bit addressing mode, an operand address and bits 40-63 of a double word, and bits 0-39 of the double word are ignored. In 31-bit addressing mode, an operand address and bits 33-63 of a double word and bits 0-32 of the double word are ignored. In 31-bit addressing mode, an operand address and bits 33-63 of a double word, and bits 0-32 of the double word are ignored. In 64-bit addressing mode, an operand address and bits 0-63 of a double word. In access record mode, access record 1 specifies the address space containing the program block token (PLT), access record B2 specifies the address space containing the second operand, and access record B4 specifies the space address containing an operating room or a list of parameters. Also, for an operand whose address is in the parameter list, an access list entry token (ALET) is in the list along with the address and is used in the access record mode to specify the address space containing the operand. In access record mode, if an access exclusion or storage change event PER is recognized for an operand whose address is in the parameter list, the associated ALET in the parameter list is loaded into access record R3 when the exclusion or event and recognized. Then, during the resulting program interruption, if a value is due to be stored as the exclude access identification at the actual location 160 or the PER access identification at the actual location 161, R3 is stored. If the instruction execution is completed without acknowledging an exception or event, the contents of the R3 access record are unpredictable. When not in the access register mode, or when a parameter list containing an ALET is not used, the contents of the access register R3 remain unchanged. Even number storage operands (2, 4, 6 and 8) must be designated in an integral limit, which is a word limit for function codes that are a multiple of 4, a double word limit for function codes that are one or 2 more than a multiple of 4, or a quadword limit for function codes that are 3 more than a multiple of 4. A list of parameters, if used, must be designated in a double word limit. Otherwise, a specification exception is recognized. The program lock token address (PLT) in general register 1 does not have a limit alignment requirement. All fields not used in a parameter list must contain all zeros; otherwise, the program may not operate compatible in the future. A serialization function is performed immediately after the lock is obtained and again immediately before being released. However, values fetched from the parameter list before the lock is obtained are not necessarily fetched again. A serialization function is not performed if the test bit, bit 55 of the general register 0, is one. Function codes 0-3 (Compare and load)
[0107] The comparison value of the first operand is compared with the second operand. When the comparison value of the first operand is equal to the second operand, the third operand is replaced by the fourth operand, and the conduction code 0 is defined. When the comparison value of the first operand is not equal to the second operand, the comparison value of the first operand is replaced by the second operand and condition code 1 is defined. Function codes 4-7 (compare and exchange)
[0108] The comparison value of the first operand is compared with the second operand. When the comparison value of the first operand is equal to the second operand, the replacement value of the first operand is stored at the location of the second operand, and the conduction code 0 is set. When the comparison value of the first operand is not equal to the second operand, the comparison value of the first operand is replaced by the second operand and condition code 1 is defined. Function codes 8-11 (Compare double and change)
[0109] The comparison value of the first operand is compared with the second operand. When the comparison value of the first operand is equal to the second operand, the comparison value of the third operand is compared to the fourth operand. When the comparison value of the third operand is equal to the fourth operand (after the comparison value of the first operand has been found to be equal to the second operand), the replacement value of the first operand is stored in the second operand location, the value of replacement of the third operand is stored at the fourth operand location, and the conduction code 0 is defined. When the comparison value of the first operand is not equal to the second operand, the comparison value of the first operand is replaced by the second operand and condition code 1 is defined. When the comparison value of the third operand is not equal to the fourth operand (after the comparison value of the first operand has been found to be equal to the second operand), the comparison value of the third operand is replaced by the fourth operand, and the condition code 2 is defined. Function codes 12-15 (compare and exchange and store)
[0110] The comparison value of the first operand is compared with the second operand. When the comparison value of the first operand is equal to the second operand, the first operand location, the third operand is stored in the fourth operand location and the conduction code 0 is set. When the comparison value of the first operand is not equal to the second operand, the comparison value of the first operand is replaced by the second operand and condition code 1 is defined. Function codes 16-19 (compare and exchange and double store)
[0111] The comparison value of the first operand is compared to the second operand. When the comparison value of the first operand is equal to the second operand, the replacement value of the first operand is stored at the second operand location, the third operand is stored at the fourth operand location, the fifth operand is stored at the sixth operand location , and condition code 0 is defined. When the comparison value of the first operand is not equal to the second operand, the comparison value of the first operand is replaced by the second operand and condition code 1 is defined. Function codes 20-23 (compare and exchange and store triple)
[0112] The comparison value of the first operand is compared with the second operand. When the comparison value of the first operand is equal to the second operand, the replacement value of the first operand is stored at the second operand location, the third operand is stored at the fourth operand location, the fifth operand is stored at the sixth operand location , the seventh operand is stored at the location of the eighth operand and conduction code 0 is defined. When the comparison value of the first operand is not equal to the second operand, the comparison value of the first operand is replaced by the second operand and condition code 1 is defined. Block
[0113] A lock is obtained at the beginning of the operation and released at the end of the operation. The obtained lock is represented by a program lock token (PLT) whose logical address is specified in the general register 1 as already described. A PLT is a value produced by a model-dependent transformation of the PLT logical address. Depending on the model, the PLT can be derived directly from the PLT logical address or, when DAT is turned on, from the actual address that results from the transformation of the PLT logical address by DAT. If DAT is used, access record translation (ART) precedes DAT in access record mode. A PLT selects one of a number depending on the model of locks in the configuration. Programs running on different CPUs can be assured of specifying the same block just by specifying logical PLT addresses that are the same and that can be transformed into the same real address by different CPUs. Since a model may or may not use ART and DAT when forming a PLT, conditions of access exclusion that may be encountered during ART and DAT may or may not be recognized as exclusions. There is no access from a location designated by a PLT, however an addressing exception can be recognized for the location. A protection exclusion is not recognized for any reason during the processing of a PLT logical address. The CPU can have one lock at a time. When RUN LOCKED OPERATION is performed by this CPU and must use a lock that is already done by another CPU due to the execution of an instruction RUN OPERATION LOCKED by the other CPU, execution by that CPU is delayed until the lock is no longer maintained. An excessive delay can be caused only by a machine malfunction and is a machine check condition. The order in which multiple requests for the same block are fulfilled is undefined. A non-recoverable failure of a CPU while maintaining a lock can result in a machine check, entering a stop checking state, or stop checking the system. Machine verification and processing backup if all operands are undamaged or processing damage if registry operands are damaged. If a machine check or stop check status is the result, none of the storage operands have been altered or all storage operands that were to be altered have been correctly altered and in any case, the lock has been released. If the storage operands are not in their correct original state or their correct final state, the result is to stop checking the system. INSTRUCTION TO PERFORM FLOATING POINT OPERATION:
[0114] When performed by a computer system, the operation specified by the function code in the general register 0 is performed and the conduction code is set to indicate the result. When there are no exceptional conditions, condition code 0 is defined. When an IEEE non-trap exception is recognized, condition code 1 is defined. When an IEEE separator deletion with alternative action is recognized, condition code 2 is defined. A 32-bit return code is placed in bits 32-63 of general register 1; bits 0-31 of general register 1 remain unchanged. The instruction EXECUTE FLOATING POINT OPERATION (PFPO) is subject to the AFP register control bit, bit 45 of the control register 0. For PFPO to be successfully executed, the AFP register control bit must be one; otherwise, a deletion of AFP record data, DXC 1, is recognized. Bit 32 of the general register 0 and the test bit. When bit 32 is zero, the function specified by bits 33-63 of the general register 0 is performed; each field in bits 33-63 must be valid and the combination must be a valid and installed function; otherwise, a specification exception is recognized. When bit 32 is one, the function specified by bits 33-63 is not performed, however, instead, the conduction code is set to indicate whether those bits specify a valid and installed function; the conduction code is set to 0 if the function is valid and installed, or to 3 if the function is invalid or not installed. This will be useful if additional features are assigned in the future. This definition is written as if the test bit was zero except when mentioned otherwise.
[0115] Bits 33-39 of GR0 specify the type of operation. Only one type of operation is currently defined: 01, hex, and Radical to Convert Floating Point PFPO. For the floating point-PFPO radical operation, other fields in the general register 0 include first operand format, second operand format, control flags and rounding method. For the floating point-PFPO radical operation, the second operand is converted to the format of the first operand and placed in the first operand location, a return code is placed in bits 32-63 of general register 1, and the condition is defined to indicate whether an exceptional condition has been recognized. The first and second operands are in implicit floating point registers. The first operand is in FPRO (paired with FPR2 for extended). The second operating is in FPR4 (paired with FPR6 for extended). Controlling alternating actuation
[0116] Bit 57 of the general register 0 and the alternating deletion action control. The definition of this control affects the action taken for IEEE overflow separator and IEEE underflow exchangings.
[0117] When the control of alternating and zero displacement action, IEEE overflow separator and IEEE subflow excesses are reported in normal mode. That is, the appropriate data deletion code (DXC) is placed in byte 2 of the floating point control register, the operation is completed, and a program interruption for data deletion occurs. (As part of the program interruption, the DXC is stored at location 147). This is called an IEEE separator excitation with normal action. When the alternating deletion action control is one, the DXC is placed in byte 2 of the floating point control register, operation is completed, condition code 2 is defined, and program execution continues with the next sequential instruction. . (There is no program interruption and the DXC is not stored at location 147.) This is called an alternating-action IEEE separator exception. HFP overflow control:
[0118] Bit 58 of the general register 0 and the HFP overflow control. When the HFP overflow control is zero, an HFP overflow condition is reported as an IEEE invalid operation exclusion and is subject to the IEEE invalid operation mask. When the HFP overflow control is one, an HFP overflow condition is reported as an IEEE overflow overflow and is subject to the IEEE overflow mask. The HFP overflow control is only defined for HFP targets; when another from an HFP target is specified, that bit must be zero. HFP subflow control:
[0119] For HFP targets, bit 59 of the general register 0 and the HFP alternate subflow control. When HFP subflow control is zero, the HFP subflow causes the result to be defined to be a true zero with the same signal that the source and subflow is not reported. (The result in this case is inaccurate and subject to the control of suppression of inaccuracy). When the HFP subflow control is one, the condition is reported as an IEEE subflow exclusion and is subject to the IEEE subflow mask. Bit 59 of the general register 0 is set for HFP and DFP targets; when a BFP target is specified, that bit must be zero. Preferred DFP quantum control (DPQC):
[0120] For DFP targets, bit 59 of the general register 0 and the preferred DFP quantum control (DPQC). For radical conversion with DFP targets, if the given value is inaccurate, the cohort element with the smallest quantum is selected; if the given value is accurate, the selection depends on bit value 59 of general register 0, the preferred quantum control DFP (DPQC). When the given value is exact and the DPQC bit is zero, the cohort element with the highest quantum is selected. When the provided value is exact and the DPQC bit is one, the preferred quantum is one and the cohort element with the quantum closest to one is selected. Return code
[0121] Regardless of which conduction code is set, and independent of whether the test bit is one, a 32-bit return code is placed in bits 32-63 of general register 1; bits 0-31 of general register 1 remain unchanged. A return code is also placed in general register 1 when a program interruption occurs for an IEEE separator deletion that is completed, • general register 1 is not updated when a program interruption occurs for an IEEE separator deletion. IEEE which suppresses. Thus, the general register 1 is updated in a program interruption for IEEE overflow, IEEE subflow and inaccurate separator excesses, however it is not updated in a program interruption for an invalid IEEE operation separator exclusion. . Except where otherwise specified, the return code is a value of zero. Signal preservation
[0122] For radical to convert PFPO floating point, the result sign is equal to the source sign. The only exception is that when the source is a NaN and the target is HFP; in this case, the result and the largest representable number in the target HFP format (Hmax) with the plus sign. Preferred Quantum
[0123] For radical conversion with DFP targets, if the value provided is inaccurate, the cohort element with the smallest quantum is selected; if the given value is accurate, the selection depends on bit value 59 of general register 0, the preferred quantum control DFP (DPQC). When the given value is exact and the DPQC bit is zero, the cohort element with the highest quantum is selected. When the provided value is exact and the DPQC bit is one, the preferred quantum is one and the cohort element with the quantum closest to one is selected. Conversion from NaN
[0124] When converting between DFP and BFP, the NaN signal is always preserved, and the payload value is preserved, when possible. If the value of the source payload exceeds the maximum value of the target payload, the target is set to the default QNaN, but with the same signal as the source. When separators are disabled, an SNaN is converted to the corresponding QNaN, and the payload is preserved, when possible; that is, SNaN (x) is converted to QNaN (x), where x is the payload value. For DFP, both QNaN (0) and SNaN (0) can be represented; however in BFP, there is a representation for QNaN (0), but not for SNaN (0). Stepped value and signal scaling exponent (Q) for PFPO
[0125] When, for the floating point-PFPO convert radical operation, the IEEE overflow separator or IEEE subflow separator occurs, the value is scaled and computed using the following steps: T = bQ Z = g + T Where Q is the signaling scaling exponent, be the target radical (2, 10 or 16), T and the scaling factor, geo rounded up to precision and ez the scaled value. The scaling exponent signaled (Q) and selected to make the magnitude of the scaled result value (z) fall within the range: 1 <| z | <b. the value of the signaling scaling exponent (Q), treated as a signaled binary integer of 32 bits, and placed in bits 32-63 of the general register 1; bits 0-31 of general register 1 remain unchanged. The scaled value is used as the supplied value and is placed in the result location. For DFP targets, the cohort element with the quantum closest to the preferred scaled and selected quantum. (However, it should be noted that for all currently supported conversions, the result is always inaccurate, so the cohort element with the smallest quantum is selected.) For BFP targets, there are no redundant representations, there is only one element in one cohort. For HFP targets, the result is normalized. HFP values
[0126] Non-normalized HFP values are accepted on entry, but all HFP results are normalized. If an HFP result was less than the smaller representable normalized number (in magnitude), an HFP underflow condition exists. Overflow and underflow from HFP to PFPO
[0127] For an HFP target of a PFPO floating point convert radical operation, the treatment of overflow and underflow conditions is controlled by the HFP overflow control and the HFP underflow control, respectively.
[0128] HFP overflow: an HFP overflow condition exists when the higher number of target accuracy HFP (Hmax) is exceeded in magnitude by the rounded precision value. That is, when the characteristic of a normalized HFP result would exceed 127 and the fraction is not zero. When the HFP overflow control is zero, the HFP overflow is reported as an invalid operation exclusion from IEEE and is subject to the IEEE invalid operation mask in the FPC registry. This is called an HFP overflow condition as an invalid IEEE operation. When the HFP overflow control is one, the HFP overflow is reported as an IEEE overflow overflow and is subject to the IEEE overflow mask in the FPC record. This is called an HFP overflow condition as an IEEE overflow.
[0129] HFP subflow: an HFP subflow condition exists when the rounded precision value is not zero and is less in magnitude than the lower normalized number of HFP target precision, Hmin. That is, when the characteristic of a normalized HFP result would be less than zero and the fraction is not zero. The result is set to a true zero with the same signal as the source. The HFP subflow condition report is subject to the HFP subflow control. The result in this case, however, is inaccurate and is subject to the controls for that condition. When the HFP underflow control is zero, the HFP underflow condition is not reported. When the HFP subflow control is one, the HFP subflow is reported as an IEEE subflow exclusion and is subject to the IEEE subflow mask in the FPC register. This is called an HFP underflow condition as an IEEE subflow. INSTRUCTION TO PERFORM TIMING FACILITY FUNCTION:
[0130] When performed by a computer system, a timing facility function specified by the function code in general register 0 is performed. The conduction code is defined to indicate the result of the function. The general register 1 contains the address of a parameter block in storage. PTFF query functions place information in the parameter block; PTFF control functions use information obtained from the parameter block. As noted by other CPUs and channel programs, references to the parameter block can be multiple access references, accesses to these storage locations are not necessarily simultaneous in block, and the sequence of these accesses or references is undefined. Bit positions 57-63 of the general register 0 contain the function code. Bit 56 of general register 0 must be zero; otherwise, a specification exception is recognized. All other bits in the general register 0 are ignored. General register 1 contains the logical address of the leftmost byte of the parameter block in storage. In 24-bit addressing mode, the contents of bit positions 40-63 of the general register 1 constitute the address and the contents of bit positions 0-39 are ignored. In the 31-bit addressing mode, the bit position contents 33-63 of the general register 1 constitute the address, and the bit position contents 032 are ignored. In 64-bit addressing mode, the contents of bit positions 0-63 of general register 1 constitute the address. The function PTFF-QAF (Functions available for consultation) provides the means of indicating the availability of the other functions. The PTFF-QAF function indicates whether the function is installed for a program running in a supervisor state at the basic machine level. PTFF-QAF (Functions available for consultation)
[0131] The parameter block used for the function has the following format: a 128-bit field is stored in the parameter block. Bits 0-127 of this field correspond to function codes 0-127, respectively, of the PTFF instructions. When a bit is one, the corresponding function is installed; otherwise, the function is not installed. Bits 0-3 of pb.wl are defined in ones, since these bits represent function codes 0-3, which are currently assigned to query functions. Bits 4-31 of pb.wl are reserved for additional query functions. Bits 0-3 of pb.w3 are defined in ones, since these bits represent function codes 64-67, which are currently assigned to control functions. Bits 4-31 of pb.w3 are reserved for additional control functions. Parameter block words pb.w2 and pb.w4 are reserved for future extensions. PTFF-QTO (TOD query offset)
[0132] The 64-bit physical clock value returned (pb.Tu) is the physical clock value in the most recent TOD offset update event. The 64-bit TOD offset value returned (pb.d) indicates the TOD offset value (d). This is the current value being added to Tr (the physical watch) to obtain Tb (the basic machine TOD watch); i.e., Tb = Tr + pb.d. The 64-bit logical TOD offset value returned (pb.dl) indicates the current value being added to Tr (the physical clock) to obtain Tc (the logical TOD clock for the current CPU execution level); i.e., Tc = Tr + pb.dl. Thus, when executed at the basic machine level, pb.dl = pb.d = d; when executed at the level of logical division, the time difference Tp-Tb (Dp) is added, resulting in pb.dl = d + Dp; and when executed at the virtual machine level, the time difference Tv-Tp (Dv) is also added, resulting in pb.dl = d + Dp + Dv. Transports (carry), if any, from bit position 0 are ignored in the addition for each of these equations. The 64-bit TOD time difference value returned (pb.ed) is the TOD time difference for the current level of CPU execution. When executed at the basic machine level, this value is zero; when executed at the level of logical division, whether the value is the time difference Tp-Tb (Dp); when executed at the virtual machine level, this value is the difference of time Tv-Tp (Dv). PTFF-QSI (Consultation address information)
[0133] The 64-bit physical clock value returned (pb.Tu) is the physical clock value in the most recent TOD offset update event. The remaining fields are the values of the old episode and new episode records. PTFF-QPT (Physical consultation clock)
[0134] The 64-bit physical watch value (bp.Tr) is the current physical watch value. Zeroes are stored for the rightmost bit positions that are not provided by the physical clock. When the watch is running, two runs of PTFF-QPT, on the same or different CPUs, do not necessarily return different values from the watch. PTFF-ATO (Adjust TOD offset)
[0135] The 64-bit value (bp) from the parameter block, treated as an unsigned binary value, is added to the base offset of the next episode. A transport, if any, from bit position 0 is ignored in this addition. The effect is not immediate, but it is programmed to coincide with the next TOD displacement update event. If the next episode has already been programmed, and has not yet become active, then the sum of bp and new.b replaces new.b and no other action is taken. If the next episode was not scheduled (that is, the new episode records are the current episode) then the new episode records are saved in the old episode records and a new episode is programmed (thereby making the old episode records the current episode). The time to start a new episode (new.s) is defined in the value that the physical watch will have in the next event of updating the displacement of TOD and the base displacement of the new episode (new.b) is defined in the sum of bp.aeo TOD's displacement value would have had at that very moment, computed using the current steering parameters. The rate of direction is not changed by this function, if a new episode is programmed, the rates of fine and thick direction of the new episode are equal to the current values. The execution of the function of adjusting TOD offset is locked so that the entire contents of the TOD offset register appear to be updated simultaneously as observed by all CPUs in the configuration. However, access to logical TOD watches (basic machine TOD watch, logical division TOD watch and virtual machine TOD watch) by CPUs in the configuration are not artificially delayed; thus, the addition of a large unsigned signal value can have the effect of a negative change and can cause TOD logical watches to appear to reverse. PTFF-STO (Set TOD offset)
[0136] The 64-bit value (pb.d) from the parameter block replaces the TOD offset. When issued at the basic machine level, the effect is not immediate, however it is programmed to coincide with the next TOD displacement update event. If the next episode has already been scheduled, and has not yet become active, then pb.d replaces new.b and no further action is taken. If the next episode has not been scheduled (that is, the new episode records are the current episode), then the new episode records are saved in the old episode records and a new episode is programmed (thereby making the episode records the current episode). The time to start a new episode (new.s) is set to the value that the physical watch will have in the next event to update TOD offset and the new episode base offset (new.b) is set to the value of pb.d. The rate of driving is not changed by this function if a new episode is programmed, the rates of fine and thick driving of new episode are equal to the current values. When issued at the logical division or virtual machine level, the function can be simulated by the hypervisor and operates at the time difference from TOD to the current level of CPU execution (Dp or Dv, respectively); no new episodes are scheduled and the change takes effect immediately. The execution of the function of defining TOD offset is locked so that the total contents of the TOD offset register appear to be updated simultaneously as observed by all CPUs in the configuration. However, access to logical TOD watches (basic machine TOD watch, logical division TOD watch and virtual machine TOD watch) by CPUs in the configuration are not artificially delayed; therefore, replacing the TOD offset with a smaller value can cause logical TOD watches to seem to go backwards. PTFF-SFS (Define fine steering rate)
[0137] The 32-bit value (bp) of the parameter block becomes the fine direction rate for the next episode. The effect is not immediate, however it is programmed to coincide with the next event of updating TOD displacement. If the next episode has already been scheduled, and has not yet become active, then pb.f replaces new.f and no further action is taken. If the next episode has not been scheduled (that is, the new episode records are the current episode), then the new episode records are saved in the old episode records and a new, scheduled episode (thereby making the episode records the current episode). The time to start a new episode (new.s) is defined in the value that the physical watch will have in the next event to update TOD offset and the base of new episode (new.b) is defined in the value that the TOD offset will have in that same instant. , computed using the current steering parameters. The rate of new episode fine (new.f) is defined in pb.f and the rate of new episode coarse is equal to the current value. When the new episode is feared, accesses to logical TOD watches by CPUs in the configuration are locked to ensure that logical TOD watches appear to be exclusive and monotonically increasing as noted by all programs. PTFF-SGS (Set coarse rate)
[0138] The 32-bit value (pb.g) of the parameter block becomes the coarse direction rate for the next episode. The effect is not immediate, however it is programmed to coincide with the next event of updating TOD displacement. If the next episode has already been scheduled, and has not yet become active, then pb.g replaces new.g and no further action is taken. If the next episode has not been scheduled (that is, the new episode records are the current episode), then the new episode records are saved in the old episode records and a new, scheduled episode (thereby making the episode records the current episode). The time to start a new episode (new.s) is defined in the value that the physical watch will have in the next event to update TOD offset and the base of new episode (new.b) is defined in the value that the TOD offset will have in that same instant. , computed using the current steering parameters. The new episode coarse rate (new.g) is defined in pb.g and the new episode coarse rate is equal to the current value. When the new episode takes effect, access to the logical TOD watches by CPUs in the configuration are locked to ensure that the logical TOD watches appear to be exclusive and monotonically increasing as observed by all programs. ISNTRUCTION BLOCKING FACILITY:
[0139] With reference to figure 8, the function of a Virtual Architecture Level Instruction Lock (VAL) facility in a VM is shown. Each instruction to be executed on the VM (as shown in the Instructions in storage column), includes an opcode. In some implementations, the opcode is a unique field in instruction 901 902 903 904. In other implementations, opcodes can be distributed in more than one field in instruction 905 (OpCode | OC) 906 (OpCode | OpCode). Preferably, circuits, microcoding or a combination thereof, would determine, based on the opcode, whether the instruction to be executed was supported or not by the current Virtual machine. If it was not supported, a program interruption, for example, a program deletion would be indicated and the instruction deleted.
[0140] In an implementation, the opcode of the instruction to be executed would be used to index an opcode table 907 to find an entry associated with the opcode. The localized entry would include a code indicating the machine level supported by the opcode. In another implementation, each Virtual machine would have an opcode table and the entry in the table would indicate whether the opcode was supported by the Virtual machine.
[0141] With reference to figure 9, the code (machine level (ML)) 1002 obtained from table 907 would be compared 1005 against a state description (IBC) entry 1008 from a state description table 1004 of the virtual machine, and if machine level code 1002 were greater than the IBC status description input 1008, the instruction would normally execute 1007, otherwise the attempt to execute would result in a program exclusion 1006. In another embodiment, instruction fields in addition to, or different from the Opcode field, they can be used to index in the 907 opcode table. For example, an opcode can have reserved fields (to be 0 or ignored) in a previous machine architecture, which are used at architectural levels newer ones to provide new function. An embodiment would include these bits with the Opcode to index in the opcode table 907. In another embodiment, the opcode table 907 can have fields in addition to the ML field used to indicate the permitted use of reserved bits in the associated instruction. For example, if the instruction has 4 reserve bits, the ML table can contain 0000 if all bits must be 0, or 1's in selected bits where a 1 indicates that previously reserved bits in the field can be 0 or 1 (allowing the recently introduced function of the VM instruction). EASY CONSULTATION / TESTING INSTRUCTION:
[0142] If a FUNCTION LOCKING FACILITY of the Instruction Query / Test facility is installed (figure 10), the opcode table entry 1001 may, in one embodiment, additionally include a function code field (Fcx) 1003 (or a pointer to a function code table 1108). Function code field 1003 (or entry 1007 of function code table 1108) is compared 1103 with the function code to be executed 1102. If the function code compares, the instruction 1105 is allowed to use the function code , if the function code does not compare 1103, the instruction execution causes a program interruption such as a program exception or specification exception (program check) 1104.
[0143] Referring to figure 11, if a QUERY BLOCKING / FUNCTION TEST FACILITY of the Query / Instruction Test facility is installed, if any query instruction 1201 is performed to determine the installed function of the instruction, only the codes of function allowed by the Virtual machine are returned 1205. In one embodiment, a significant 1108 bit table is provided for the Virtual machine that is used by the virtual machine to answer such queries. In another embodiment, a mask is provided (not shown) for the Virtual machine to be ANDed with the function codes installed from the host machine to create a result of allowed function codes 1107 of the instruction in the VM.
[0144] Referring to figure 8, example z / Architecture instruction formats are shown. The 901 format shows a 2-byte format in which the Opcode (Op) occupies the high order byte, and general register fields R1 and R2 occupy 4 respective bits of the remaining byte. The 902 format shows a 2-byte Opcode instruction format only. The 903 format shows an instruction of 4 bytes (word) having an Opcode of 1 byte (Op) followed by 3 record fields (R1, C2 and B2) and then an immediate field called the Displacement field (D2). The 904 format shows a 4-byte instruction having a 4-byte Opcode (Op), followed by a 4-bit record field (B2) and then a 12-bit Immediate field (I2). The 905 format shows a 4-byte instruction having a 2-byte Opcode (Op) followed by a 4-bit M1 mask, followed by a 4-bit Opcode extension (Op) and a reserved 4-bit field, followed by a Immediate 12-bit field (I2). The 906 format shows an instruction of 6 bytes having an Opcode of 1 byte (Op) followed by 3 record fields, (R1, X2 and B2) and then an immediate field called the Displacement field (DL2) followed by an immediate field 8-bit (DH2) and an 8-bit Opcode extension (Op).
[0145] With reference to figures 8 and 9, in one embodiment, when an instruction is sought for execution by a logical processor of a virtual machine, an opcode Table 907 is searched, using the Operational Code (s) ( is) of the instruction as a search argument. If an entry is found 1001 for the instruction, the entry includes information 1002 1003 to determine instruction permission information. In a preferred embodiment, an entry includes a field 1002 that specifies a code (ML) indicating the machine level of the architecture supporting the instruction. A status description 1004 is provided for each VM. The state description includes a field (IBC) 1005 that represents the machine level of the architecture that the VM should simulate. If 1005, the machine level of the architecture that supports the instruction (ML) is higher than the machine level of the architecture that the VM must simulate (IBC), a program exclusion (program verification) is signaled, and in one embodiment , the execution of the instruction can be suppressed. On the other hand, if the architecture machine level supporting the instruction (ML) is not higher than the architecture machine level that the VM must simulate (IBC), the instruction is allowed to execute.
[0146] In some environments, instructions are provided that are capable of carrying out any of a plurality of functions (such as the CYCLE MESSAGE instruction described above). The selection of the function by an instruction may be by means of specifying a function code (FC) representing the function. The function code can be indirectly specified by the instruction or explicitly specified by bits or fields of the instruction, for example. In some cases, certain function codes can be initially implemented (0-3, for example) at a machine architecture level, and additional function codes can be added at later machine architecture levels. The VM can be equipped with the ability to only allow function codes to run at an older architectural level.
[0147] Referring to figure 10, this can be accomplished by having a function code field (FCx) 1003 in opcode table entry 1001. When an instruction is to be executed, the FCx field 1003 specifies the code list of function allowed to be returned instead of the effective function codes supported by the Host processor. In the embodiment, the FCx 1003 field of the Opcode Table entry is concatenated with the IBC 1005 field to index in an FCx Table 1108 to locate an entry that comprises allowed function codes (FCs) 1107. The allowed FCs 1107 are compared to the FC specified by instruction 1102 (in the Encrypt message instruction, bits 1102 of general register 0 1101 contain the specified FC (1102). If 1103 the FC value is allowed 1105, normal execution of the function represented by the FC bits is allowed. If 1103 the FC value 1104 is not allowed, a program exclusion event (program check) is executed. Similarly, when performing a function operation / Query function 1201 (such as the CODE MESSAGE instruction Query operation), the FCX bits of the Opcode table entry 1103 are concatenated 1106 with the IBC bits 1105 to index in the FCX table to locate the permitted FCs 1107 for the instruction whose Opcode finds the opcode table entry 1101. The FCs per then 1105 are returned to the location specified by the function Test / Query operation.
[0148] In one embodiment, when the FCX bits are 0, no FCx 1108 Table access is performed and any function code indicated by the corresponding instruction is used without translation.
[0149] In one embodiment, other architectural changes to the instructions can use the same mechanism as described for function codes. In this case, for example, instruction 905 at an architectural level has the bits between the Opcode extension field and the reserved I2 field (0000). Preferably, the reserved bits are tested to 0’s to make sure that the instruction will perform properly in an environment where non-zero bits support an unsupported function yet. A newer architecture implements a new function using one or more of the reserved bits to identify the new function. In an example, these 4 reserved bits (Res) can be indexed in Table FCx 1108 to determine if they are supported as shown for FC 1102 bits in figure 10. In this case, the concatenation would be 0 | | IBC | | FCx for Fungao codes, and 1 | | IBC | | FCx for the new function permission test 1103. Rather than FC 1102 being compared to allowed FCs 1107, the Res field of instruction 905 would be checked against allowed FCS bits 1107 to determine 1103 whether the function is allowed.
[0150] In another embodiment, the Res field of instruction 905 could be concatenated as if it were a third Opcode extension of 905 Opcodes to index in the Opcode Table 907 to determine whether the function introduced with the field is allowed.
[0151] As part of, or subsequent to, searching for an instruction, a CPU can determine certain attributes of the instruction, for example, number of operands, type of operands (storage or record), operand alignment requirements, and authorization requirements . In an emulation environment, this determination may be the result of a simple table query using the operation code as an index; on a high-performance CPU, the determination can be embedded in the processor instruction decode circuitry.
[0152] The level and virtual architecture facility introduces an additional attribute associated with each instruction: the machine level at which the instruction was first introduced in the architecture. This machine level can be a numeric point encoded in a continue (for example, 10.2 meaning the 10th generation machine in the second firmware level), or it can simply be a value relative to the most recent machine level (for example, 2 [or - 2], meaning that the instruction was introduced two generations before the current machine).
[0153] With reference to figure 12 in one embodiment, installed functions selected from a multi-function instruction are hidden, the multi-function instruction designed to perform a function of a plurality of installed functions, the concealment comprising setting 1201 a value by controlling availability of installed functions for a multi-function instruction from a Host computer comprising one or more processors, a processor having a first plurality of installed functions from the multi-function instruction, the first plurality of installed functions comprising one or more first installed functions and one or more second functions installed, and executing 1201 a multi-function instruction, the multi-function instruction comprising an opcode field, the execution comprises responsive to the multi-function instruction specifying a query function, execute the query function to determine installed functions disp levels for the instruction of multiple functions; executing the query function uses the value to determine one or more second installed functions; and the query function execution stores 1203 a result value indicating that one or more of one or more second installed functions are not available for the instruction of multiple functions.
[0154] With reference to figure 13, in one embodiment, the value is defined 1301 by a hypervisor of the Host computer for a virtual machine of the Host computer, the virtual machine comprising one or more logical processors, one or more logical processors being assigned ^ connected to one or more physical processors, a physical processor having one or more second functions installed from the multi-function instruction, wherein the multi-function instruction is performed on the virtual machine by a logical processor of one or more logical processors on a physical processor of one or more physical processors.
[0155] In one embodiment, one or more second functions installed is determined 1302 based on the opcode of the multi-function instruction.
[0156] With reference to figure 14, in one embodiment, the hypervisor having set 1201 a control value on a virtual machine, defines 1401 another value controlling the availability of installed functions for an instruction of multiple functions running on another virtual machine of the system computer host; and another multi-function instruction is executed 1402 on the other virtual machine by another logical processor from one or more other logical processors; responsive to another multi-function instruction specifying another query function, the other query function is performed to determine installed functions available for the other multi-function instruction; the other query function execution uses the other value to determine one or more installed third functions; and the other query function execution stores 1403 another result value indicating that one or more of one or more third functions installed are not available for the other multi-function instruction.
[0157] In one embodiment, the stored result value is a significant bit value, where each bit position corresponds to a function, and a bit being 1 indicates that the corresponding function is installed.
[0158] With reference to figure 15, in one embodiment, the query function is specified by a specified multi-function instruction function code 1501 or a specified multi-function instruction test bit 1502.
[0159] Referring to figure 16, in one embodiment, the multi-function instruction is a zArchitecture instruction consisting of any one of a 1601 cryptographic instruction, a Run Facility Timing Instruction instruction, figure 17 any of 1701 instruction of Execute floating point operation or an instruction of Execute blocked operation, in which the cryptographic instruction comprises any one of an instruction of Encrypt message, an instruction of Compute intermediate message, an instruction of Compute Digest of last message, an instruction of Compute Digest last message, an instruction to Compute message authentication code, wherein the instruction for multiple functions specifies a query function; is responsive to the instruction of multiple functions being a cryptographic instruction of a PTFF instruction, the function code specified for instruction of multiple functions to be executed and obtained 1602, the function code obtained consisting of 1605 in a query function, in which the value gives result 1604 is stored based on a control value and a plurality of bits, each bit of the plurality of bits indicating whether a corresponding function code is supported; It is responsive to the instruction of multiple functions being a cryptographic instruction or a PTFF instruction, the function code specified for instruction of multiple functions to be executed and obtained, the function code obtained not being the query function 1605, a cryptographic function or a PTFF function and executed 1603 according to the obtained function code; and 1701 is responsive to the instruction of multiple functions with the instruction of Execute Operation blocked or the instruction of Execute floating point operation and the test bit specified for the instruction of multiple functions and 1 1702, a determination 1704 is made if a function code specified for multi-function instruction and installed based on the control value, where the stored result value 1704 is a conduction code value; It is responsive to the instruction of multiple functions with the instruction of Execute Operation blocked or the instruction of Execute floating point operation and the test bit specified for instruction of multiple functions and 0 1702, a floating point function or a blocked and executed operation 1703 according to the obtained function code.
[0160] In one embodiment, responsive to the instruction of multiple functions specifying a non-consultation function of the first plurality of installed functions, responsive to the non-consultation function being one of the second installed functions, the non-consultation function is executed and responsive to the function non-consultation function being a function different from one of the second installed functions, performance of the non-consultation function is blocked.
[0161] The above may be useful in understanding the terminology and structure of a computer system embodiment. The embodiments may not be limited to z / Architecture or the description provided therein. The embodiments can be advantageously applied to other computer architectures from other computer manufacturers with the teaching of the present invention.
[0162] While preferred embodiments have been illustrated and described here, it should be understood that embodiments may not be limited to the precise construction disclosed herein, and the right may be reserved for all changes and modifications within the scope of the invention as defined in the appended claims. .

权利要求:
Claims (10)
[0001]
1. Computer-implemented method to hide selected installed functions from a multifunctional instruction, the multifunctional instruction being designed to be executed by a single processor to make the single processor perform a single function of a plurality of installed functions, the only function being identified by the multifunctional instruction, the plurality of installed functions comprising a query function to discover installed functions and one or more functions not related to the query to operate on operands of a multifunctional instruction, the method characterized by the fact that it comprises: defining, by a hypervisor, a control value configured to control the availability of functions installed in multifunctional instructions of a virtual machine of a host computer comprising one or more processors, each of said one or more processors being configured to execute each of a plurality of said the installed functions, the plurality of installed functions comprising one or more first installed functions and one or more second installed functions, the hypervisor being configured to create virtual machines; and based on the control value, make the one or more first installed functions of a processor unavailable for multifunctional instructions of the virtual machine and make the one or more second installed functions of the processor available for the multifunctional instructions of the virtual machine; and executing a multifunctional instruction by the virtual machine, the multifunctional instruction comprising an opcode field and specifying a single function to be executed from the plurality of installed functions, the multifunctional instruction being configured to select any one of a plurality of functions, including a query function and one or more non-query functions, the execution of the multifunctional instruction comprising: based on the multifunctional instruction that specifies a query function as the only function to be executed, execute the query function, the execution of the query function comprising x) -y): x) use the control value to determine that one or more first installed features are not available and that one or more installed features are available; and y) storing a result value, the stored result value indicating that the one or more first installed functions are not available for multifunctional instructions for the virtual machine and that the one or more second installed functions are available for multifunctional instructions for the virtual machine; and based on the multifunctional instruction that specifies a non-query function as the only function to be performed, execute the no-query function which comprises a) -c): a) use the control value to determine that one or more first functions installed are not available and that one or more installed features are available; b) based on the non-consultation function being one of the said second functions installed, execute the non-consultation function; and c) based on the non-query function being one of the first functions installed, prevent the execution of the referred non-query function so that it is not executed on the virtual machine, on the hardware or otherwise.
[0002]
2. Method, according to claim 1, characterized by the fact that the virtual machine comprises one or more logical processors, one or more logical processors being assigned to one or more physical processors, a physical processor with the plurality of installed functions of the multifunctional instruction, wherein the multifunctional instruction is performed on the virtual machine by a logical processor of one or more logical processors in a physical processor of one or more physical processors.
[0003]
3. Method according to claim 2, characterized in that the one or more first functions installed from a processor is not available for multifunctional instruction and one or more second functions installed from the processor available for multifunctional instruction is based in the operation code of the multifunctional instruction.
[0004]
4. Method, according to claim 2, characterized by the fact that it comprises: defining, by the hypervisor, another control value configured to control the availability of the functions installed in a multifunctional instruction running on another virtual machine of the host computer; and based on the other control value, make one or more third-party functions installed from one processor unavailable for another multifunctional instruction and one or more fourth-party functions installed from the processor available to the other multifunctional instruction; and executing the other multifunctional instruction on the other virtual machine by another logical processor from one or more other logical processors, the other multifunctional instruction comprising another opcode field; based on the other multifunctional instruction that specifies another query function, perform the other query function, the realization of the other query function comprising: using the other control value to determine that the one or more thirds installed functions are not available and the one or more installed fourth functions are available; and storing another result value indicating that the one or more installed third functions are not available for the other multifunctional instruction and the one or more installed fourth functions are available for the other multifunctional instruction.
[0005]
5. Method, according to claim 2, characterized by the fact that the value of the stored result is a bit insignificant, where each bit position corresponds to a function and a bit being 1 indicates that the corresponding function is available for multifunctional instructions.
[0006]
6. Method according to claim 2, characterized by the fact that the function is specified by any one of a corresponding function code specified by the multifunctional instruction and a corresponding bit specified by the multifunctional instruction.
[0007]
7. Method, according to claim 6, characterized by the fact that the multifunctional instruction is a z / Architecture instruction that consists of any of the cryptographic instructions, an Execute Timing Facility Function (PTFF) instruction, an Execute Operation of Floating Point is an Execute Blocked Instruction instruction, where the cryptographic instruction comprises any of the instructions Encrypt Message, Encrypt Message with Chaining, a Compute Digest Intermediate Message instruction, a Compute Digest of Last Message instruction and a Compute Authentication Code instruction from Message, and in which the execution of the multifunctional instruction comprises: based on the multifunctional instruction be a cryptographic instruction or PTFF, obtain the function code specified by the multifunctional instruction to be executed and execute f) -g) comprising: f) based on function code obtained, specify the query function, where the value of the stored result and a plurality of bits, each bit of the plurality of bits indicating whether a corresponding function is available for the multifunctional instruction, the corresponding function being any one of a cryptographic function and a PTFF function; and g) based on the function code obtained, specify the non-query function, perform any of the cryptographic and PTFF functions according to the function code obtained; and based on the multifunctional instruction, with the Execute Operation Blocked instruction or the Perform Floating Point Operation instruction and a test bit specified as 1, determining that a specified multifunctional instruction function is installed, where the stored result value is one condition code value; and based on the multifunctional instruction the Execute Operation Locked instruction or the Execute Floating Point Operation instruction and the test bit specified as 0, perform a Floating Point operation or a blocked operation according to the obtained function code.
[0008]
8. Method, according to claim 1, characterized by the fact that blocking the performance of said non-consultation function comprises blocking the execution of the multifunctional instruction.
[0009]
9. Method, according to claim 8, characterized by the fact that the execution of blocking of the multifunctional instruction comprises causing a program exception event, the program exception comprising a program interruption in an operating system program.
[0010]
10. Method implemented by computer to hide selected installed functions from a multifunctional instruction, the multifunctional instruction being designed to be executed by a single processor to make the single processor perform a single function of a plurality of installed functions, the only function being identified by the multifunctional instruction, the plurality of installed functions comprising one or more functions not related to consultation to operate on operands of a multifunctional instruction, the method characterized by the fact that it comprises: defining, by a hypervisor, a control value configured to control the availability of functions installed in multifunctional instruments of a virtual machine of a host computer comprising one or more processors, each of said one or more processors being configured to execute each of a plurality of said installed functions, the plurality of installed functions comprising one or more first functions installed and one or more second functions installed, the hypervisor being configured to create virtual machines; and based on the control value, making the one or more first installed functions of a processor unavailable for multifunctional instructions of the virtual machine and making the one or more second installed functions of the processor available for the multifunctional instructions of the virtual machine; and executing a multifunctional instruction by the virtual machine, the multifunctional instruction comprising an opcode field and specifying a single function to be executed from the plurality of installed functions, the multifunctional instruction being configured to select any one of a plurality of functions, including one or more functions without consultation, the execution of the multifunctional instruction comprising: based on the multifunctional instruction that specifies a non-consultation function as the only function to be executed, executing the non-consultation function comprising a) -c): a) use the value control to determine that one or more first installed features are not available and that one or more installed features are available; b) based on the non-consultation function, being one of the said second functions installed, executing the non-consultation function; and c) based on the non-query function being one of the first installed functions, to prevent the execution of said non-query function so that it is not executed on the virtual machine, on the hardware or otherwise.

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法律状态:
2019-01-08| B06F| Objections, documents and/or translations needed after an examination request according [chapter 6.6 patent gazette]|

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2019-08-13| B06U| Preliminary requirement: requests with searches performed by other patent offices: procedure suspended [chapter 6.21 patent gazette]|

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2020-07-21| B09A| Decision: intention to grant [chapter 9.1 patent gazette]|

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2020-12-01| B16A| Patent or certificate of addition of invention granted [chapter 16.1 patent gazette]|Free format text: PRAZO DE VALIDADE: 10 (DEZ) ANOS CONTADOS A PARTIR DE 01/12/2020, OBSERVADAS AS CONDICOES LEGAIS. |

优先权:

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申请号 | 申请日 | 专利标题

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US12/822,358|US9851969B2|2010-06-24|2010-06-24|Function virtualization facility for function query of a processor|

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US12/822,358|2010-06-24|

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PCT/EP2010/067046|WO2011160724A1|2010-06-24|2010-11-08|Function virtualization facility for function query of a processor|

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